D at a S h e e t , D S 1 , M ay 2 00 0
DSCC4
DMA Supported Serial
Communication Controller with 4
Channels
PEB 20534 Version 2.1
PEF 20534 Version 2.1
Datacom
N e v e r
s t o p
t h i n k i n g .
PEB 20534
PEF 20534
Revision History:
Previous Version:
Page
Page
(in previous (in current
Version)
Version)
-
429-438
-
427-435
Current Version: 2000-05-30
Data Sheet 09.98 (V 2.0)
Subjects (major changes since last revision)
removed remaining references to command bit GCMDR:IADC
corrected timing values #81-#86, #132, #149
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at
http://www.infineon.com
Edition 2000-05-30
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 5/30/00.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEB 20534
PEF 20534
Preface
The
DMA Supported Serial Communication Controller with 4 Channels
(DSCC4) is a
Multi Protocol Controller for a wide range of data communication and telecommunication
applications. This document provides complete reference information on hardware and
software related issues as well as on general operation.
Organization of this Document
This Data Sheet is divided into 15 chapters. It is organized as follows:
• Chapter 1, Overview
Gives a general description of the product, lists the key features, and presents some
typical applications.
• Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
• Chapters 3,4,5,6,7 Functional Description
These chapters provide detailed descriptions of all DSCC4 internal function blocks.
• Chapter 8, Detailed Protocol Descriptions
Gives a detailed description of all protocols supported by the serial communication
controllers SCCs.
• Chapter 9, Reset and Initialization Procedure
Gives examples for DSCC4 initialization procedure and operation.
• Chapter 10, Detailed Register Description
Gives a detailed description of all DSCC4 on chip registers.
• Chapter 11, Host Memory Organization
Provides an overview of all DSCC4 data structures located in the shared memory
• Chapter 12, JTAG Boundary Scan
Gives a detailed description of the boundary scan unit.
• Chapter 13, Electrical Characteristics
Gives a detailed description of all electrical DC and AC characteristics and provides
timing diagrams and values for all interfaces.
• Chapter 14, Package Outline
Data Sheet
3
2000-05-30
PEB 20534
PEF 20534
Data Sheet
4
2000-05-30
PEB 20534
PEF 20534
Table of Contents
1
1.1
1.2
1.2.1
1.2.2
1.3
1.4
1.4.1
1.4.1.1
1.4.1.2
1.4.1.3
2
2.1
2.2
3
4
4.1
4.1.1
4.1.2
4.2
5
5.1
5.1.1
5.1.2
5.1.2.1
5.1.2.2
5.1.2.3
5.1.2.4
5.1.3
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
6
6.1
6.1.1
Page
18
19
22
22
22
23
24
26
26
27
28
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differences between the DSCC4 and the ESCC Family . . . . . . . . . . . . . .
Enhancements to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . .
Simplifications to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HSSI Application - DCE Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HSSI Application - DTE Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Data Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Microprocessor Bus Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Configuration Space Register Overview . . . . . . . . . . . . . . . . . . . . .
De-multiplexed Bus Interface Extension . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller and Central FIFOs
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Control and Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Transmit Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Receive Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Operation Using Hold-Bit Control Mechanism . . . . . . . . . . . .
DMAC Operation Using Last Descriptor Address Control Mode . . . .
DMAC Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central FIFOs Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central FIFO Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Transmit FIFO (TFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Receive FIFO (RFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Internal Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMAC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Little / Big Endian Byte Swap Convention . . . . . . . . . . . . . . . . . . . . . . .
51
51
51
52
53
57
59
59
64
66
71
76
78
81
85
85
89
92
93
94
95
Multi Function Port (MFP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Local Bus Interface (LBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
LBI Bus Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data Sheet
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2000-05-30
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