Freescale Semiconductor, Inc.
Product Brief
MMC2114PB/D
Rev. 0, 6/2002
MMC2114 M•CORE
Microcontroller Product Brief
(also addresses MMC2113)
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This document is an overview of the 32-bit MMC2114 and MMC2113 M•CORE
microcontrollers, focusing on their highly integrated and diverse feature set. It includes
general and detailed descriptions of features and of the various modules incorporated in these
devices, and lists packaging, tools, and ordering information for the family.
The MMC2114 and MMC2113 are members of a family of general-purpose microcontroller
units (MCU) based on the M•CORE M210 central processor unit (CPU). The M•CORE M210
CPU architecture is one of the most compact, full 32-bit core implementations available. The
pipelined reduced instruction set computer (RISC) execution unit uses 16-bit instructions to
achieve maximum speed and code efficiency, while conserving on-chip memory resources.
The instruction set is designed to support high-level language implementation. A
non-intrusive resident debugging system supports product development and in-situ testing.
Unless otherwise noted, all references to MMC2114 also apply to the MMC2113.
The main features of the M•CORE M210 CPU architecture are:
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32-bit load/store RISC architecture
Fixed 16-bit instruction length
13 32-bit control register file
32 32-bit general-purpose register file
Availability of alternate file set of 32 32-bit general purpose registers
Efficient 4-stage execution pipeline
Single-cycle execution for most instructions, 2-cycle branches and memory accesses
Support for byte/half-word/word memory access
Support for both normal and fast interrupts
Vectored and autovectored interrupt support
On-chip emulation support (OnCE)
Full static design for minimal power consumption
The M•CORE CPU also benefits applications requiring low power consumption. Total system
power consumption is determined by all the system components, rather than the CPU alone.
In particular, memory power consumption (both on-chip and external) is a dominant factor in
total power consumption of the CPU plus memory subsystem. With this in mind, the CPU
instruction set architecture trades absolute performance capability for reduced total energy
consumption. This is accomplished while maintaining a high level of performance at a given
clock frequency.
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Features Overview
1.1
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Features Overview
M•CORE M210 integer processor
256 Kbytes (MMC2114) or 128 Kbytes (MMC2113) FLASH memory
32 Kbytes (MMC2114) or 8 Kbytes (MMC2113) of static random-access memory (SRAM)
Serial peripheral interface (SPI)
Two serial communications interfaces (SCI)
Two timers
Queued analog-to-digital converter (QADC)
43-source interrupt controller with support for 8 external interrupt pins
Two periodic interval timers
Watchdog timer
Phase-locked loop (PLL)
Integrated low-voltage detector (LVD)
General-purpose input/output (GPIO)
Multiple chip configurations including single-chip or expanded mode operation
7 sources of reset
External bus interface supporting multiple data widths
OnCE/Joint Test Action Group (JTAG) support for debug and system-level board testing
The MMC2114 and MMC2113 are the next devices in a family of devices that began with the MMC2107.
The devices in this family are highly integrated with on-chip modules and include the following features:
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The 32-bit MMC2114, with its microRISC central processing unit, delivers 31 Dhrystone 2.1 MIPS
performance at 33 MHz.
Figure 1 shows a block diagram of the main modules on the MMC2114.
2
MMC2114 M•CORE Microcontroller Product Brief
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Features Overview
V
STBY
TRST
TCLK
TMS
TDI
TDO
DE
V
DDF
JTAG
TAP
SRAM
8 KBYTES (MMC2113)
32 KBYTES (MMC2114)
FLASH
128 KBYTES (MMC2113)
256 KBYTES (MMC2114)
V
SSF
D[31:0]
EXTERNAL MEMORY INTERFACE
A[22:0]
R/W
EB[3:0]
CS[3:0]
TC[2:0]
SHS
CSE[1:0]
TA
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OnCE
CPU
CPU BUS
IPBUS
INTERFACE
PSTAT[3:0]
PROGRAMMABLE
INTERVAL
TIMER 1
INTERRUPT
CONTROLLER
PROGRAMMABLE
INTERVAL
TIMER 2
WATCHDOG
TIMER
OSC/PLL
TEST
CS
PORTS
TEA
OE
TEST
EXTAL
XTAL
CLKOUT
PLLEN
POR
RESET
LVD
RESET
RSTOUT
V
SS
x 8
V
DD
x 8
INT[7:0]
EDGE
PORT
IPBUS
V
RL
, V
RH
TIM1
TIM2
SCI1
SCI2
SPI
ADC
V
DDA
, V
SSA
V
DDH
ICOC1[3:0]
ICOC2[3:0]
PQB[3:0]
Figure 1. MMC2114 Block Diagram
3
MMC2114 M•CORE Microcontroller Product Brief
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PQA[4:3]
PQA[1:0]
TXD1
RXD1
TXD2
RXD2
MISO
MOSI
SCK
SS
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Enhancements over the MMC2107
1.2
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Enhancements over the MMC2107
Improved type of FLASH
. The MMC2114 uses Second Generation FLASH for M
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CORE
(SGFM), which has five distinct advantages over the MMC2107’s CDR MoneT FLASH (CMFR)
technology.
— No externally applied programming voltage
— Simpler programming and erasing algorithms and shorter programming time
— A sophisticated security mechanism
— A three-way code protection scheme
— Higher endurance
Several important enhancements have been incorporated into the MMC2114 from its predecessor, the
MMC2107. These enhancements are as follows:
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More FLASH.
The MMC2114 has twice as much FLASH as that found in the MMC2107 (the
MMC2113 has the same amount of FLASH as the MMC2107 at 128 Kbytes), and allows
execution of code in one array to program the other array.
More static random-access memory (SRAM)
. The MMC2114 has four times the amount of
MMC2107 (the MMC2113 has the same amount at 8 Kbytes).
LVD circuit.
The MMC2114 offer a low-voltage detection (LVD) monitor, which, upon the
sensing of a low-voltage V
DD
state, allows the central processor unit (CPU) to either cause an
interrupt from normal program flow and take appropriate action, or reset the device.
5V-tolerant inputs.
The digital input/output (I/O) ports on the MMC2114 have been made more
flexible by allowing up to 5 volts to be applied to all pins configured as inputs without danger of
damage to the port or to the device.
New package.
Along with the 100-pin and 144-pin low-profile quad flat pack (LQFP) packages
offered for the MMC2107, the MMC2114 is also offered in a very compact 196-ball plastic mold
array process ball grid array (MAPBGA). This package has the same pinout features as those in
the 144-pin LQFP.
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1.3
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Feature List
M•CORE M210 integer processor:
— 32-bit reduced instruction set computer (RISC) architecture
— Low power and high performance
The following lists the major features of the MMC2114 and MMC2113:
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OnCE debug support
128 Kbytes (MMC2113) or 256 Kbytes (MMC2114) FLASH memory:
— Single-cycle byte, half-word (16-bit) and word (32-bit) reads
— Fast automated program and erase procedure with interrupt support
— Ability to program one FLASH bank while executing from another (MMC2114 only)
— Flexible protection scheme for accidental program/erase
— Access restriction controls for both supervisor/user and data/program spaces
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MMC2114 M•CORE Microcontroller Product Brief
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Feature List
— Enhanced security feature prevents unauthorized access to contents of FLASH (protects
company IP)
— Single-supply operation (no need for separate, high voltage program/erase supply)
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8 Kbytes (MMC2113) or 32 Kbytes (MMC2114) of static random-access memory (SRAM):
— Single cycle byte, half-word (16-bit), and word (32-bit) reads and writes
— Standby power supply support
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Serial peripheral interface (SPI):
— Master mode and slave mode with slave select output
— Serial clock with programmable polarity and phase
— Control of SPI operation during wait mode
— Mode fault error flag with CPU interrupt capability
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— Wired-OR mode and reduced drive control
— General-purpose input/output (I/O) capability
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Two serial communications interfaces (SCI):
— Full-duplex operation
— Standard mark/space non-return-to-zero (NRZ) format
— 13-bit baud rate prescaler
— Programmable 8-bit or 9-bit data format
— Separately enabled transmitter and receiver
— Separate receiver and transmitter CPU interrupt requests
— Two receiver wakeup methods (idle line and address mark)
— Hardware parity checking
— Receiver framing error and 1/16 bit-time noise detection
— Reduced drive control
— General-purpose I/O capability
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Two timers:
— Four 16-bit input capture/output compare channels
— 16-bit pulse accumulator
— Pulse widths variable from microseconds to seconds
— Eight selectable timer prescalers
— Toggle-on-overflow feature for pulse-width modulation
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Queued analog-to-digital converter (QADC):
— Eight analog input channels
— 10-bit resolution ±2 counts accuracy
— Minimum 7 µS conversion time
— Programmable input sample time for various source impedances
— Two conversion command queues with a total of 64 entries
— Subqueues possible using pause mechanism
5
MMC2114 M•CORE Microcontroller Product Brief
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