C8051F39x/37x
50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU
Analog Peripherals
(‘F390/2/4/6/8 and ‘F370/4)
-
10-Bit ADC
•
Programmable throughput up to 500 ksps
•
Up to 16 external inputs, programmable as single-
•
•
-
-
-
•
•
•
•
ended or differential
Reference from on-chip voltage reference, V
DD
or
external VREF pin
Internal or external start of conversion sources
Supports output through resets for continuous
operation
Programmable hysteresis and response time
Configurable as interrupt or reset source
Accurate to ±2
°
C across temperature range with no
user calibration
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
-
-
Memory
-
Up to 1 kB internal data RAM (256 + 768)
-
Up to 16 kB Flash; In-system programmable in 512-
-
byte Sectors
512 bytes of byte-programmable EEPROM; 1 mil-
lion write/erase cycles (‘F37x)
instructions in 1 or 2 system clocks
Up to 50 MIPS throughput with 50 MHz clock
Expanded interrupt handler
Two 10-Bit Current Output DACs
Comparator
Precision Temperature Sensor
Digital Peripherals
-
21 or 17 Port I/O
-
UART, 2 SMBus (I
2
C compatible), and SPI serial
-
-
ports
Six general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules and PWM functionality
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping,
inspect/modify memory and registers
Low Power
-
160 µA/MHz Active mode with 49 MHz internal
-
Temperature Range
-
–40 to +85 °C (‘F37x)
-
–40 to +105 °C (‘F39x)
Package
-
24-Pin QFN (‘F390/1/4/5 and ‘F37x)
-
20-Pin QFN (‘F392/3/6/7/8/9)
precision oscillator
200 nA Stop mode current
Clock Sources
-
49 MHz ±2% precision internal oscillator
•
Supports crystal-less UART operation
•
Low-power suspend mode with fast wake time
-
80 kHz low-frequency, low-power oscillator
-
External oscillator: Crystal, RC, C, or CMOS clock
-
Can switch between clock sources on-the-fly; useful
in power saving modes
Supply Voltage 1.8 to 3.6 V
-
Built-in voltage supply monitor
ANALOG
PERIPHERALS
A
M
U
X
+
–
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
SMBus0
SMBus1
SPI
PCA0
PCA1
PCA2
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Port 0
CROSSBAR
Port 1
P2.0
P2.1–
P2.4*
*P2.1–2.4 QFN24 Only
10-bit
500 ksps
ADC
VREF
10-bit
10-bit
Current
Current
DAC
DAC
Temp Sensor
Precision
Temp Sensor
‘F390/2/4/6/8 &
‘F370/4 Only
49 MHz PRECISION
INTERNAL OSCILLATOR
80 KHz LOW FREQUENCY
INTERNAL OSCILLATOR
512 B
EEPROM
HIGH-SPEED CONTROLLER CORE
16/8 kB
8051 CPU
1024 B
ISP FLASH
(50 MIPS)
SRAM
FLEXIBLE
DEBUG
POR WDT
INTERRUPTS
CIRCUITRY
Rev. 1.0 12/12
Copyright © 2012 by Silicon Laboratories
C8051F39x/37x
C8051F39x/37x
Table of Contents
1. System Overview ..................................................................................................... 17
2. Ordering Information ............................................................................................... 20
3. C8051F33x Compatibility ........................................................................................ 21
3.1. Hardware Incompatibilities ................................................................................ 21
4. Pin Definitions.......................................................................................................... 22
5. QFN-20 Package Specifications ............................................................................. 28
6. QFN-24 Package Specifications ............................................................................. 30
7. Electrical Characteristics ........................................................................................ 32
7.1. Absolute Maximum Specifications..................................................................... 32
7.2. Electrical Characteristics ................................................................................... 33
7.3. Typical Performance Curves ............................................................................. 45
8. Precision Temperature Sensor
(C8051F390/2/4/6/8 and C8051F370/4 Only)............................................................... 47
8.1. Temperature in Two’s Complement .................................................................. 47
9. 10-Bit ADC (ADC0, C8051F390/2/4/6/8 and C8051F370/4 Only) ........................... 50
9.1. Output Code Formatting .................................................................................... 51
9.2. Modes of Operation ........................................................................................... 52
9.2.1. Starting a Conversion................................................................................ 52
9.2.2. Tracking Modes......................................................................................... 53
9.2.3. Settling Time Requirements...................................................................... 54
9.3. Programmable Window Detector....................................................................... 58
9.3.1. Window Detector Example........................................................................ 60
9.4. ADC0 Analog Multiplexer (C8051F390/2/4/6/8 and C8051F370/4 Only) .......... 61
10. Temperature Sensor (C8051F390/2/4/6/8 and C8051F370/4 Only)..................... 64
10.1. Calibration ....................................................................................................... 65
11. 10-Bit Current Mode DACs (IDA0, IDA1, C8051F390/2/4/6/8 and
C8051F370/4 Only) ....................................................................................................... 66
11.1. IDAC Output Scheduling ................................................................................. 66
11.1.1. Update Output On-Demand .................................................................... 66
11.1.2. Update Output Based on Timer Overflow ............................................... 68
11.1.3. Update Output Based on CNVSTR Edge ............................................... 68
11.2. IDAC Reset Behavior ...................................................................................... 68
11.3. IDAC Output Mapping ..................................................................................... 68
12. Voltage Reference Options ................................................................................... 73
13. Voltage Regulator .................................................................................................. 75
13.1. Power Modes................................................................................................... 75
14. Comparator0........................................................................................................... 76
14.1. Comparator Multiplexer ................................................................................... 80
15. CIP-51 Microcontroller........................................................................................... 82
15.1. Instruction Set.................................................................................................. 83
15.1.1. Instruction and CPU Timing .................................................................... 83
15.2. CIP-51 Register Descriptions .......................................................................... 87
16. Prefetch Engine...................................................................................................... 92
Rev. 1.0
3
C8051F39x/37x
17. Memory Organization ............................................................................................ 93
17.1. Program Memory............................................................................................. 94
17.1.1. MOVX Instruction and Program Memory ................................................ 94
17.2. Data Memory ................................................................................................... 94
17.2.1. Internal RAM ........................................................................................... 94
17.2.1.1. General Purpose Registers ............................................................ 95
17.2.1.2. Bit Addressable Locations .............................................................. 95
17.2.1.3. Stack ............................................................................................ 95
17.2.2. External RAM .......................................................................................... 95
18. Device ID Registers ............................................................................................... 97
19. Special Function Registers................................................................................. 101
19.1. SFR Paging ................................................................................................... 101
19.2. Interrupts and Automatic SFR Paging ........................................................... 101
19.3. SFR Page Stack Example ............................................................................. 103
20. Interrupts .............................................................................................................. 117
20.1. MCU Interrupt Sources and Vectors.............................................................. 118
20.1.1. Interrupt Priorities.................................................................................. 118
20.1.2. Interrupt Latency ................................................................................... 118
20.2. Interrupt Register Descriptions ...................................................................... 120
20.3. External Interrupts INT0 and INT1................................................................. 128
21. Flash Memory....................................................................................................... 131
21.1. Programming The Flash Memory .................................................................. 131
21.1.1. Flash Lock and Key Functions .............................................................. 131
21.1.2. Flash Erase Procedure ......................................................................... 131
21.1.3. Flash Write Procedure .......................................................................... 132
21.2. Non-volatile Data Storage ............................................................................. 132
21.3. Security Options ............................................................................................ 133
21.4. Flash Write and Erase Guidelines ................................................................. 135
21.4.1. V
DD
Maintenance and the V
DD
Monitor ................................................ 135
21.4.2. PSWE Maintenance .............................................................................. 135
21.4.3. System Clock ........................................................................................ 136
22. EEPROM (C8051F37x) ......................................................................................... 140
22.1. EEPROM Communication Protocol.............................................................. 140
22.1.1. Slave Address Byte............................................................................... 141
22.1.2. Acknowledgement (ACK) ...................................................................... 141
22.1.3. Not-Acknowledgement (NACK)............................................................. 141
22.1.4. Reset..................................................................................................... 141
22.2. Write Operation ............................................................................................. 142
22.3. Read Operation ............................................................................................. 143
22.3.1. Current Address Read .......................................................................... 143
22.3.2. Selective Address Read........................................................................ 145
23. Cyclic Redundancy Check Unit (CRC0)............................................................. 147
23.1. CRC Algorithm............................................................................................... 147
23.2. Preparing for a CRC Calculation ................................................................... 149
23.3. Performing a CRC Calculation ...................................................................... 149
4
Rev. 1.0
C8051F39x/37x
23.4. Accessing the CRC0 Result .......................................................................... 149
23.5. CRC0 Bit Reverse Feature............................................................................ 149
24. Reset Sources ...................................................................................................... 155
24.1. Power-On Reset ............................................................................................ 156
24.2. Power-Fail Reset / VDD Monitor ................................................................... 157
24.3. External Reset ............................................................................................... 159
24.4. Missing Clock Detector Reset ....................................................................... 159
24.5. Comparator0 Reset ....................................................................................... 159
24.6. PCA Watchdog Timer Reset ......................................................................... 159
24.7. Flash Error Reset .......................................................................................... 159
24.8. Software Reset .............................................................................................. 159
25. Power Management Modes................................................................................. 161
25.1. Idle Mode....................................................................................................... 161
25.2. Stop Mode ..................................................................................................... 162
25.3. Suspend Mode .............................................................................................. 162
26. Oscillators and Clock Selection ......................................................................... 164
26.1. System Clock Selection................................................................................. 165
26.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 166
26.2.1. Internal Oscillator Suspend Mode ......................................................... 166
26.3. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 168
26.3.1. Calibrating the Internal L-F Oscillator.................................................... 168
26.4. Internal Low-Power Oscillator........................................................................ 169
26.5. External Oscillator Drive Circuit..................................................................... 169
26.5.1. External Crystal Mode........................................................................... 169
26.5.2. External RC Example............................................................................ 171
26.5.3. External Capacitor Example.................................................................. 171
27. Port Input/Output ................................................................................................. 173
27.1. Port I/O Modes of Operation.......................................................................... 174
27.1.1. Port Pins Configured for Analog I/O...................................................... 174
27.1.2. Port Pins Configured For Digital I/O...................................................... 174
27.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 175
27.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 175
27.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 176
27.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 177
27.3. Priority Crossbar Decoder ............................................................................. 178
27.4. Port I/O Initialization ...................................................................................... 180
27.5. Port Match ..................................................................................................... 183
27.6. Special Function Registers for Accessing and Configuring Port I/O ............. 185
28. SMBus0 and SMBus1 (I2C Compatible)............................................................. 192
28.1. Supporting Documents .................................................................................. 193
28.2. SMBus Configuration..................................................................................... 193
28.3. SMBus Operation .......................................................................................... 193
28.3.1. Transmitter vs. Receiver ....................................................................... 194
28.3.2. Arbitration.............................................................................................. 194
28.3.3. Clock Low Extension............................................................................. 194
Rev. 1.0
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DSP and ARM Processors
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