MT8870DSR1-1 datasheet, PDF - EEWORLD Datasheet

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MT8870DSR1-1: DescriptionIC receiver dtmf 18soic; CategoryWireless rf/communication Telecom circuit; File Size414KB，19 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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MT8870DSR1-1 Overview

IC receiver dtmf 18soic

MT8870DSR1-1 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	SOIC
package instruction	SOP, SOP18,.4
Contacts	18
Reach Compliance Code	compliant
JESD-30 code	R-PDSO-G18
JESD-609 code	e3
length	11.55 mm
Number of functions	1
Number of terminals	18
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP18,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum slew rate	9 mA
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	DTMF SIGNALING CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm

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MT8870D/MT8870D-1

ISO

-CMOS

Integrated DTMF Receiver

Data Sheet

Features

•

Complete DTMF Receiver

Low power consumption

Internal gain setting amplifier

Adjustable guard time

Central office quality

Power-down mode

Inhibit mode

Backward compatible with MT8870C/MT8870C-1

MT8870DE

MT8870DS

MT8870DN

MT8870DSR

MT8870DNR

MT8870DN1

MT8870DE1

MT8870DS1

MT8870DNR1

MT8870DSR1

MT8870DE1-1

MT8870DS1-1

MT8870DSR1-1

October 2006

Ordering Information

18 Pin PDIP

18 Pin SOIC

20 Pin SSOP

18 Pin SOIC

20 Pin SSOP

20 Pin SSOP*

18 Pin PDIP*

18 Pin SOIC*

20 Pin SSOP*

18 Pin SOIC*

18 Pin PDIP*

18 Pin SOIC*

*Pb Free Matte Tin

Tubes

Tape &

Tubes

Tape &

Tubes

Tape &

Reel

Applications

•

Receiver system for British Telecom (BT) or

CEPT Spec (MT8870D-1)

Paging systems

Repeater systems/mobile radio

Credit card systems

Remote control

Personal computers

Telephone answering machine

VDD

VSS

VRef

INH

-40°C to +85°C

Description

The MT8870D/MT8870D-1 is a complete DTMF

receiver integrating both the bandsplit filter and digital

decoder functions. The filter section uses switched

capacitor techniques for high and low group filters;

the decoder uses digital counting techniques to detect

and decode all 16 DTMF tone-pairs into a 4-bit code.

PWDN

Bias

Circuit

VRef

Buffer

High Group

Filter

Dial

Tone

Filter

Low Group

Filter

Zero Crossing

Detectors

Digital

Detection

Algorithm

Code

Converter

and Latch

Chip Chip

Power Bias

IN +

IN -

to all

Chip

Clocks

Steering

Logic

OSC1

OSC2

St/GT

ESt

STD

TOE

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT8870D/MT8870D-1

Decoder Section

Data Sheet

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the

incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm

protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency

deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of

immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the

detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry

specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition

will cause ESt to assume an inactive state (see “Steering Circuit”).

St/GT

ESt

StD

MT8870D/

MT8870D-1

GTA

=(RC)In(V

TSt

)

GTP

=(RC)In[V

/(V

-V

TSt

)]

Figure 4 - Basic Steering Circuit

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character

recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt

causes v

(see Figure 4) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains

high) for the validation period (t

GTP

), v

reaches the threshold (V

TSt

) of the steering logic to register the tone pair,

latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and

drives v

to V

. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the

output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been

registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state

control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between

signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal

interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting

the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system

requirements.

Guard Time Adjustment

In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown

in Figure 4 is applicable. Component values are chosen according to the formula:

REC

GTP

GTA

Zarlink Semiconductor Inc.

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