8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
• Eleven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Eight main memory blocks
• Smart 3 technology (B3):
3.3V ±0.3V
V
CC
3.3V ±0.3V
V
PP
application programming
5V ±10%
V
PP
application/production programming1
• Compatible with 0.3µm Smart 3 device
• Advanced 0.18µm CMOS floating-gate process
• Address access time: 90ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• TSOP, SOP and FBGA packaging options
• Byte- or word-wide READ and WRITE
(MT28F800B3): 1 Meg x 8/512K x 16
MT28F008B3
MT28F800B3
3V ONLY, DUAL SUPPLY (SMART 3)
40-Pin TSOP Type I
48-Pin TSOP Type I
44-Pin SOP
GENERAL DESCRIPTION
The MT28F008B3 (x8) and MT28F800B3 (x16/x8)
are low-voltage, nonvolatile, electrically block-eras-
able (flash), programmable memory devices contain-
ing 8,388,608 bits organized as 524,288 words (16 bits)
or 1,048,576 bytes (8 bits). Writing and erasing the
device is done with a V
PP
voltage of either 3.3V or 5V,
while all operations are performed with a 3.3V V
CC
.
Due to process technology advances, 5V V
PP
is optimal
for application and production programming. These
devices are fabricated with Micron’s advanced 0.18µm
CMOS floating-gate process.
The MT28F008B3 and MT28F800B3 are organized
into eleven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure
or overwrite, the devices feature a hardware-protected
boot block. This block may be used to store code
implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.
Options
• Timing
90ns access
• Configurations
1 Meg x 8
512K x 16/1 Meg x 8
• Boot Block Starting Word Address
Top (7FFFFh)
Bottom (00000h)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
• Packages
MT28F008B3
Plastic 40-pin (standard) TSOP Type I
Plastic 40-pin (lead free) TSOP Type I
MT28F800B3
Plastic 48-pin (standard) TSOP Type I
Plastic 48-pin (lead free) TSOP Type I
Plastic 44-pin (standard) SOP
Plastic 44-pin (lead free) SOP
NOTE:
Marking
-9
MT28F008B3
MT28F800B3
T
B
None
ET
VG
VP
WG
WP
SG
2
SP
2
1. This generation of devices does not support 12V
V
PP
production programming; however, 5V VPP
application production programming can be
used with no loss of performance.
2. Contact Factory for availability
Part Number Example:
MT28F800B3WG-9
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
1
©2001 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Figure 1: Pin Assignment (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
V
PP
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
V
PP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-Pin SOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
ORDER NUMBER AND PART MARKING
MT28F800B3WG-9 B MT28F800B3WP-9 B
MT28F800B3WG-9 T MT28F800B3WP-9 T
MT28F800B3WG-9 BET MT28F800B3WP-9 BET
MT28F800B3WG-9 TET MT28F800B3WP-9 TET
ORDER NUMBER AND PART MARKING
MT28F800B3SG-9 B
MT28F800B3SP-9 B
MT28F800B3SG-9 T
MT28F800B3SP-9 T
MT28F800B3SG-9 BET MT28F800B3SP-9 BET
MT28F800B3SG-9 TET MT28F800B3SP-9 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
V
PP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F008B3VG-9 B
MT28F008B3VP-9 B
MT28F008B3VG-9 T
MT28F008B3VP-9 T
MT28F008B3VG-9 BET MT28F008B3VP-9 BET
MT28F008B3VG-9 TET MT28F008B3VP-9 TET
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
2
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
Figure 2: Functional Block Diagran
8
Input
Buffer
BYTE#
2
I/O
Control
Logic
16KB Boot Block
Addr.
7
Input
Buffer
A0–A18/(A19)
A9
Buffer/
Latch
19 (20)
10
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
16
Input Data
Latch/Mux
A-1
Input
Buffer
X - Decoder/Block Erase Control
9
(10)
Addr.
Power
(Current)
Control
Counter
DQ15/(A - 1)
2
DQ8–DQ14
2
WP#
1
CE#
OE#
WE#
RP#
V
CC
Command
Execution
Logic
State
Machine
Y-
Decoder
7
Y - Select Gates
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
DQ0–DQ7
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
3
V
PP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.All rights reserved.
V
PP
Switch/
Pump
Output
Buffer
DQ15
Status
Register
Identification
Register
7
Output
Buffer
8
Output
Buffer
MUX
8
NOTE:
1. Does not apply to MT28F800B3SG.
2. Does not apply to MT28F008B3.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Table 1:
44-PIN
SOP
NUMBERS
43
Pin Descriptions
40-PIN
TSOP
NUMBERS
9
48-PIN
TSOP
NUMBERS
11
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle.
If WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1 (3.3V) or V
PPH
2 (5V) and RP# = V
IH
during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on
other blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status
register, sets the internal state machine (ISM) to the array
read mode and places the device in deep power-down
mode. All inputs, including CE#, are “Don’t Care,” and all
outputs are High-Z. RP# unlocks the boot block and
overrides the condition of WP# when at V
HH
(12V), and
must be held at V
IH
during all other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active
through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-
Z, and all data is accessed through DQ0–DQ7. DQ15/(A-1)
becomes the least significant address input.
Address Inputs: Select a unique 16-bit word or 8-bit byte.
The DQ15/(A-1) input becomes the lowest order address
when BYTE# = LOW (MT28F800B3) to allow for a selection
of an 8-bit byte from the 1,048,576 available.
–
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
33
24
–
28
47
OE#
BYTE#
Input
Input
11, 10, 9, 8,
7, 6, 5, 4,
42, 41, 40,
39, 38, 37,
36, 35, 34,
3, 2
31
21, 20, 19,
25, 24, 23,
18, 17, 16,
22, 21, 20,
15, 14, 8, 7, 19, 18, 8, 7,
36, 6, 5, 4, 6, 5, 4, 3, 2,
3, 2, 1, 40, 1, 48, 17, 16
13, 37
–
45
A0–A18/
(A19)
Input
DQ15/
(A-1)
DQ0–
DQ7
DQ8–
DQ14
V
PP
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
25, 26, 27,
28, 32, 33,
34, 35
–
11
29, 31, 33,
35, 38, 40,
42, 44
30, 32, 34,
36, 39, 41,
43
13
23
13, 32
–
30, 31
23, 39
29,38
37
27, 46
9,10,15
Vcc
V
SS
NC
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input:
Output LSB of address input when BYTE# = LOW during READ or
WRITE operation.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE. These pins are used to
input commands to the CEL.
Input/ Data I/Os: Data output pins during any READ operation or
Output data input pins during a WRITE when BYTE# = HIGH. These
pins are High-Z when BYTE# is LOW.
Supply Write/Erase Supply Voltage: From a WRITE or ERASE
CONFIRM until completion of the WRITE or ERASE, V
PP
must be at V
PPH
1 (3.3V) or V
PPH
2 (5V). V
PP
= “Don’t Care”
during all other operations.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
–
NoConnect:Thesepinsmaybedrivenorleftunconnected.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
Table 2:
Truth Table (MT28F800B3)
1
RP#
CE#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OE# WE# WP#
X
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
X
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
H
X
H
X
X
X
X
X
X
X
BYTE#
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
H
H
L
L
X
H
L
H
L
H
L
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
A9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
FUNCTION
V
PP
X
X
X
X
X
X
V
PPH
X
V
PPH
V
PPH
X
X
V
PPH
V
PPH
X
V
PPH
V
PPH
V
PPH
v
X
X
X
X
X
X
X
DQ0–
DQ7
High-Z
High-Z
DQ8–
DQ14
High-Z
High-Z
DQ15/
A-1
High-Z
High-Z
H
Standby
L
RESET
READ
H
READ (word mode)
H
READ (byte mode)
H
Output Disable
WRITE/ERASE (EXCEPT BOOT BLOCK)
2
H
ERASE SETUP
3
H
ERASE CONFIRM
H
WRITE SETUP
4
H
WRITE (word mode)
H
WRITE (byte mode)
4
5
H
READ ARRAY
WRITE/ERASE (BOOT BLOCK)
2, 7
H
ERASE SETUP
V
HH
ERASE CONFIRM
3
3, 6
H
ERASE CONFIRM
H
WRITE SETUP
4
V
HH
WRITE (word mode)
4, 6
H
WRITE (word mode)
V
HH
WRITE (byte mode)
4
4, 6
H
WRITE (byte mode)
H
READ ARRAY
5
DEVICE IDENTIFICATION
8, 9
Manufacturer Compatibility
(word mode)
10
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)
10
Device (byte mode, top boot)
Device (word mode, bottom
boot)
10
Device (byte mode, bottom
boot)
NOTE:
Data-Out Data-Out Data-Out
Data-Out
High-Z
A-1
High-Z
High-Z
High-Z
20h
D0h
10h/40h
Data-In
Data-In
FFh
20h
D0h
D0h
10h/40h
Data-In
Data-In
Data-In
Data-In
FFh
89h
89h
9Ch
9Ch
9Dh
9Dh
X
X
X
Data-In
X
X
X
X
X
X
Data-In
Data-In
X
X
X
00h
High-Z
88h
High-Z
88h
High-Z
X
X
X
Data-In
A-1
X
X
X
X
X
Data-In
Data-In
A-1
A-1
X
–
X
–
X
–
X
H
H
H
H
H
H
1. L = V
IL
(LOW), H = V
IH
(HIGH), X = V
IL
or V
IH
(“Don’t Care”).
2. V
PPH
= V
PPH
1 = 3.3V or V
PPH
2 = 5V.
3. Operation must be preceded by ERASE SETUP command.
4. Operation must be preceded by WRITE SETUP command.
5. The READ ARRAY command must be issued before reading the array after writing or erasing.
6. When WP# = V
IH
, RP# may be at V
IH
or V
HH
.
7. V
HH
= 12V.
8. V
ID
= 12V; may also be read by issuing the IDENTIFY DEVICE command.
9. A1–A8, A10–A18 = V
IL
.
10. Value reflects DQ8–DQ15.
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
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