MC74LCX573MELG datasheet, PDF - EEWORLD Datasheet

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MC74LCX573MELG: DescriptionIC latch transp oct LV 20-soeiaj; Categorylogic logic; File Size111KB，9 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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MC74LCX573MELG Overview

IC latch transp oct LV 20-soeiaj

MC74LCX573MELG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	SOP, SOP20,.3
Contacts	20
Reach Compliance Code	unknown
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G20
JESD-609 code	e4
length	12.575 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.024 A
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.3
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
method of packing	RAIL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	8 ns
propagation delay (tpd)	10.5 ns
Certification status	Not Qualified
Maximum seat height	2.05 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	5.275 mm
Base Number Matches	1

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MC74LCX573

Low-Voltage CMOS

Octal Transparent Latch

Flow Through Pinout

With 5 V-Tolerant Inputs and Outputs

(3-State, Non-Inverting)

The MC74LCX573 is a high performance, non-inverting octal

transparent latch operating from a 2.3 to 3.6 V supply. High

impedance TTL compatible inputs significantly reduce current

loading to input drivers while TTL compatible outputs offer improved

switching noise performance. A V

specification of 5.5 V allows

MC74LCX573 inputs to be safely driven from 5.0 V devices.

The MC74LCX573 contains 8 D-type latches with 3-state standard

outputs. When the Latch Enable (LE) input is HIGH, data on the Dn

inputs enters the latches. In this condition, the latches are transparent,

i.e., a latch output will change state each time its D input changes.

When LE is LOW, the latches store the information that was present

on the D inputs a setup time preceding the HIGH-to-LOW transition

of LE. The 3-state standard outputs are controlled by the Output

Enable (OE) input. When OE is LOW, the standard outputs are

enabled. When OE is HIGH, the standard outputs are in the high

impedance state, but this does not interfere with new data entering into

the latches. The LCX573 flow through design facilitates easy PC

board layout.

Features

http://onsemi.com

MARKING

DIAGRAMS

LCX573

AWLYYWWG

SOIC-20

DW SUFFIX

CASE 751D

TSSOP-20

DT SUFFIX

CASE 948E

LCX

573

ALYWG

•

Designed for 2.3 to 3.6 V V

Operation

5.0 V Tolerant - Interface Capability With 5.0 V TTL Logic

Supports Live Insertion and Withdrawal

OFF

Specification Guarantees High Impedance When V

= 0 V

LVTTL Compatible

LVCMOS Compatible

24 mA Balanced Output Sink and Source Capability

SOEIAJ-20

M SUFFIX

CASE 967

74LCX573

AWLYWWG

Near Zero Static Supply Current in All Three Logic States (10

mA)

Substantially Reduces System Power Requirements

•

Latchup Performance Exceeds 500 mA

•

ESD Performance:

Human Body Model >2000 V

Machine Model >200 V

•

Pb-Free Packages are Available

Assembly Location

L, WL

Wafer Lot

Y, YY

Year

W, WW =

Work Week

= Pb-Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

Semiconductor Components Industries, LLC, 2008

March, 2008 - Rev. 8

Publication Order Number:

MC74LCX573/D

MC74LCX573MELG Related Products

	MC74LCX573MELG	MC74LCX573DTG
Description	IC latch transp oct LV 20-soeiaj	Voltage-Power: 2V ~ 3.6V Logic type: D-type transparent latch Output type: Tri-state Series: 74LCX
Is it Rohs certified?	conform to	conform to
Maker	ON Semiconductor	ON Semiconductor
Parts packaging code	SOIC	TSSOP
package instruction	SOP, SOP20,.3	TSSOP, TSSOP20,.25
Contacts	20	20
Reach Compliance Code	unknown	compliant
series	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G20	R-PDSO-G20
JESD-609 code	e4	e4
length	12.575 mm	6.5 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	BUS DRIVER	BUS DRIVER
MaximumI(ol)	0.024 A	0.024 A
Number of digits	8	8
Number of functions	1	1
Number of ports	2	2
Number of terminals	20	20
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP
Encapsulate equivalent code	SOP20,.3	TSSOP20,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	RAIL	RAIL
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	8 ns	8 ns
propagation delay (tpd)	10.5 ns	10.5 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.05 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	40	40
width	5.275 mm	4.4 mm
Base Number Matches	1	1

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