NS
ESI G
WD
R N E ODU CT
O
®
PR
ED F
E N D TI TU TE
M
BS
COM
T RE IBLE SU L88013
O
N
S
IS
Data Sheet
PO S
X4163, X4165
16K, 2K x 8 Bit
November 26, 2007
FN8120.2
CPU Supervisor with 16K EEPROM
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 16Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
—8 Ld SOIC
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X4163, X4165 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Serial EEPROM Memory in one
package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
falls below the set minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Four industry
standard V
TRIP
thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
Status
Register
EEPROM Array
RESET (X4163)
RESET (X4165)
Reset &
Watchdog
Timebase
Watchdog
Timer Reset
SCL
S0
S1
2Kb
V
CC
V
TRIP
+
-
Power on and
Low Voltage
Reset
Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X4163, X4165
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X4163S8-4.5A
PART
MARKING
X4163 AL
PART NUMBER
RESET
(ACTIVE HIGH)
X4165S8-4.5A
X4165S8Z-4.5A
(Note)
X4165S8I-4.5A
X4165S8IZ-4.5A
(Note)
X4165V8-4.5A
X4165V8Z-4.5A
(Note)
X4165V8I-4.5A
X4165V8IZ-4.5A
(Note)
X4165S8-2.7
X4165S8Z-2.7
(Note)
X4165S8I-2.7
X4165S8IZ-2.7
(Note)
X4165V8-2.7
X4165V8Z-2.7
(Note)
X4165V8I-2.7
X4165V8IZ-2.7
(Note)
X4165S8-2.7A
X4165S8Z-2.7A
(Note)
X4165S8I-2.7A
X4165S8IZ-2.7A
(Note)
X4165V8-2.7A
X4165V8Z-2.7A
(Note)
X4165V8I-2.7A
X4165V8IZ-2.7A
(Note)
PART
MARKING
X4165 AL
X4165 Z AL
X4165 AM
X4165 Z AM
4165AL
4165AL Z
4165AM
4165AM Z
X4165 F
X4165 Z F
X4165 G
X4165 Z G
4165F
4165F Z
4165G
4165G Z
X4165 AN
X4165 Z AN
X4165 AP
X4165 Z AP
4165AN
4165AN Z
4165AP
4165AP Z
2.7-5.5
2.85-3.0
2.7-5.5
2.85-3.0
2.7-5.5
2.55-2.7
V
CC
RANGE
(V)
4.5-5.5
V
TRIP
RANGE (V)
4.5-4.75
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld TSSOP
(4.4mm)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4163S8Z-4.5A X4163 Z AL
(Note)
X4163S8I-4.5A
X4163 AM
X4163S8IZ-4.5A X4163 Z AM
(Note)
X4163V8-4.5A
4163AL
X4163V8Z-4.5A 4163AL Z
(Note)
X4163V8I-4.5A
4163AM
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
X4163V8IZ-4.5A 4163AM Z
(Note)
X4163S8-2.7
X4163S8Z-2.7
(Note)
X4163S8I-2.7
X4163S8IZ-2.7
(Note)
X4163V8-2.7
X4163V8Z-2.7
(Note)
X4163V8I-2.7
X4163V8IZ-2.7
(Note)
X4163S8-2.7A*
X4163 F
X4163 Z F
X4163 G
X4163 Z G
4163F
4163F Z
4163G
4163G Z
X4163 AN
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld TSSOP
(4.4mm)
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld TSSOP
(4.4mm)
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4163S8Z-2.7A* X4163 Z AN
(Note)
X4163S8I-2.7A
X4163 AP
X4163S8IZ-2.7A X4163 Z AP
(Note)
X4163V8-2.7A
4163AN
X4163V8Z-2.7A 4163AN Z
(Note)
X4163V8I-2.7A
4163AP
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
X4163V8IZ-2.7A 4163AP Z
(Note)
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
2
FN8120.2
November 26, 2007
X4163, X4165
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X4163S8
X4163S8Z
(Note)
X4163S8I
X4163S8IZ
(Note)
X4163V8
X4163V8Z
(Note)
X4163V8I
X4163V8IZ
(Note)
PART
MARKING
X4163
X4163 Z
X4163 I
X4163 Z I
4163
4163
4163I
4163I Z
PART NUMBER
RESET
(ACTIVE HIGH)
X4165S8*
X4165S8Z*
(Note)
X4165S8I
X4165S8IZ
(Note)
X4165V8
PART
MARKING
X4165
X4165 Z
X4165 I
X4165 Z I
4165
V
CC
RANGE
(V)
4.5-5.5
V
TRIP
RANGE (V)
4.25-4.5
TEMP
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld TSSOP
(4.4mm)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X4165V8Z (Note) 4165
X4165V8I
X4165V8IZ
(Note)
4165I
4165I Z
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
8 Ld TSSOP
(4.4mm)
M8.173
8 Ld TSSOP
M8.173
(4.4mm) (Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN8120.2
November 26, 2007
X4163, X4165
PIN CONFIGURATION
8 Ld JEDEC SOIC
S
0
S
1
RESET/RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
WP
V
CC
S
0
S
1
8 Ld TSSOP
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RESET/RESET
PIN FUNCTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
0
S
1
Device Select Input
Device Select Input
Function
RESET/
RESET
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain
active until V
CC
rises above the minimum V
CC
sense level for 250ms.
RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET
goes active on power up and remains active for 250ms after the power supply sta-
bilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
4
5
6
7
V
SS
SDA
6
7
8
8
1
2
SCL
WP
V
CC
4
FN8120.2
November 26, 2007
X4163, X4165
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X4163, X4165 activates a
Power On Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
It prevents the system microprocessor from starting to
operate with insufficient voltage.
It prevents the processor from operating prior to stabilization
of the oscillator.
It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
It prevents communication to the EEPROM, greatly reducing
the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP
threshold value for
200ms (nominal) the circuit releases RESET/RESET allowing
the system to begin operation.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
microprocessor must periodically send a start bit followed by
a stop bit prior to the expiration of the watchdog time out
period to prevent a RESET/RESET signal. The start and
stop bits need to be separated by SCL toggling low then high
at least one time.
The state of two nonvolatile control bits in the Status
Register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be “locked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
THRESHOLD RESET PROCEDURE
The X4163, X4165 is shipped with a standard V
CC
threshold (V
TRIP
) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard V
TRIP
is not
exactly right, or if higher precision is needed in the
V
TRIP
value, the X4163, X4165 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
LOW VOLTAGE MONITORING
During operation, the X4163, X4165 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls below a
preset minimum V
TRIP
. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP
for 200ms.
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
values WEL bit set)
WP
0 1 2 3 4 5 6 7
SCL
V
P
= 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SDA
A0h
00h
01h
00h
5
FN8120.2
November 26, 2007
京公网安备 11010802033920号
EEWORLD
