HD64F3039TE datasheet, PDF - EEWORLD Datasheet

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HD64F3039TE: DescriptionMicrocontroller, 32-Bit, FLASH, H8/300H CPU, 18MHz, CMOS, PQFP80, TQFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，690 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD64F3039TE Overview

Microcontroller, 32-Bit, FLASH, H8/300H CPU, 18MHz, CMOS, PQFP80, TQFP-80

HD64F3039TE Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	TFQFP, TQFP80,.55SQ
Contacts	80
Reach Compliance Code	unknown
Has ADC	YES
Address bus width	24
bit size	32
CPU series	H8/300H
maximum clock frequency	18 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQFP-G80
length	12 mm
Number of I/O lines	63
Number of terminals	80
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP80,.55SQ
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	4096
rom(word)	65536
ROM programmability	FLASH
Maximum seat height	1.2 mm
speed	18 MHz
Maximum slew rate	70 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	12 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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To all our customers

Regarding the change of names mentioned in the document, such as

Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were

transferred to Renesas Technology Corporation on April 1st 2003.

These operations include microcomputer, logic, analog and discrete devices,

and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,

and other Hitachi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp.

Thank you for your understanding. Except for our corporate trademark,

logo and corporate statement, no changes whatsoever have been made to the

contents of the document, and these changes do not constitute any alteration

to the contents of the document itself.

Renesas Technology Home Page: www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

Renesas Technology Corp.

Contents

Section 1

1.1

1.2

1.3

Overview

...........................................................................................................

1.4

Overview............................................................................................................................

Block Diagram...................................................................................................................

Pin Description ..................................................................................................................

1.3.1 Pin Arrangement ..................................................................................................

1.3.2 Pin Functions........................................................................................................

Pin Functions .....................................................................................................................

Section 2

2.1

CPU

..................................................................................................................... 15

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Overview............................................................................................................................

2.1.1 Features ................................................................................................................

2.1.2 Differences from H8/300 CPU.............................................................................

CPU Operating Modes ......................................................................................................

Address Space....................................................................................................................

Register Configuration ......................................................................................................

2.4.1 Overview ..............................................................................................................

2.4.2 General Registers..................................................................................................

2.4.3 Control Registers..................................................................................................

2.4.4 Initial CPU Register Values .................................................................................

Data Formats......................................................................................................................

2.5.1 General Register Data Formats ............................................................................

2.5.2 Memory Data Formats..........................................................................................

Instruction Set....................................................................................................................

2.6.1 Instruction Set Overview......................................................................................

2.6.2 Instructions and Addressing Modes .....................................................................

2.6.3 Tables of Instructions Classified by Function......................................................

2.6.4 Basic Instruction Formats.....................................................................................

2.6.5 Notes on Use of Bit Manipulation Instructions....................................................

Addressing Modes and Effective Address Calculation .....................................................

2.7.1 Addressing Modes................................................................................................

2.7.2 Effective Address Calculation..............................................................................

Processing States ...............................................................................................................

2.8.1 Overview ..............................................................................................................

2.8.2 Program Execution State......................................................................................

2.8.3 Exception-Handling State ....................................................................................

2.8.4 Exception-Handling Sequences............................................................................

2.8.5 Reset State ............................................................................................................

2.8.6 Power-Down State................................................................................................

Basic Operational Timing..................................................................................................

2.9.1

2.9.2

2.9.3

2.9.4

Overview ..............................................................................................................

On-Chip Memory Access Timing ........................................................................

On-Chip Supporting Module Access Timing.......................................................

Access to External Address Space .......................................................................

Section 3

3.1

MCU Operating Modes

............................................................................... 55

3.2

3.3

3.4

3.5

3.6

3.7

Overview............................................................................................................................ 55

3.1.1 Operating Mode Selection.................................................................................... 55

3.1.2 Register Configuration ......................................................................................... 56

Mode Control Register (MDCR) ....................................................................................... 57

System Control Register (SYSCR).................................................................................... 58

Operating Mode Descriptions............................................................................................ 60

3.4.1 Mode 1.................................................................................................................. 60

3.4.2 Mode 3.................................................................................................................. 60

3.4.3 Mode 5.................................................................................................................. 60

3.4.4 Mode 6.................................................................................................................. 60

3.4.5 Mode 7.................................................................................................................. 60

Pin Functions in Each Operating Mode............................................................................. 61

Memory Map in Each Operating Mode............................................................................. 61

Restrictions on Use of Mode 6 .......................................................................................... 70

Section 4

4.1

Exception Handling

...................................................................................... 73

4.2

4.3

4.4

4.5

4.6

Overview............................................................................................................................

4.1.1 Exception Handling Types and Priority ...............................................................

4.1.2 Exception Handling Operation .............................................................................

4.1.3 Exception Vector Table........................................................................................

Reset ..................................................................................................................................

4.2.1 Overview ..............................................................................................................

4.2.2 Reset Sequence.....................................................................................................

4.2.3 Interrupts after Reset ............................................................................................

Interrupts............................................................................................................................

Trap Instruction .................................................................................................................

Stack Status after Exception Handling ..............................................................................

Notes on Stack Usage........................................................................................................

Section 5

5.1

Interrupt Controller

....................................................................................... 81

5.2

Overview............................................................................................................................ 81

5.1.1 Features ................................................................................................................ 81

5.1.2 Block Diagram...................................................................................................... 82

5.1.3 Pin Configuration ................................................................................................. 83

5.1.4 Register Configuration ......................................................................................... 83

Register Descriptions......................................................................................................... 84

5.2.1 System Control Register (SYSCR) ...................................................................... 84

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