Ultra Series
™
Crystal Oscillator
Si540 Data Sheet
Ultra Low Jitter Any-Frequency XO (125 fs), 0.2 to 1500 MHz
KEY FEATURES
The Si540 Ultra Series
™
oscillator utilizes Silicon Laboratories’ advanced 4
th
generation DSPLL
®
technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is factory-programmed to any frequency
from 0.2 to 1500 MHz with <1 ppb resolution and maintains exceptionally low
jitter for both integer and fractional frequencies across its operating range. The
Si540 offers excellent reliability and frequency stability as well as guaranteed
aging performance. On-chip power supply filtering provides industry-leading power
supply noise rejection, simplifying the task of generating low jitter clocks in noisy
systems that use switched-mode power supplies. Offered in industry-standard
footprints, the Si540 has a dramatically simplified supply chain that enables Silicon
Labs to ship custom frequency samples 1-2 weeks after receipt of order. Unlike
a traditional XO, where a different crystal is required for each output frequency,
the Si540 uses one simple crystal and a DSPLL IC-based approach to provide
the desired output frequency. This process also guarantees 100% electrical testing
of every device. The Si540 is factory-configurable for a wide variety of user specifi-
cations, including frequency, output format, and OE pin location/polarity. Specific
configurations are factory-programmed at time of shipment, eliminating the long
lead times associated with custom oscillators.
Pin Assignments
• Available with any frequency from 0.2 MHz to
1500 MHz
• Very low jitter: 125 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSNR and supply noise immunity:
–80 dBc Typ
• 7 ppm stability option (-40 to 85C)
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 2.5×3.2, 3.2×5, 5x7 mm package options
• Any custom frequency available with 1-2
week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast video
VDD
CLK-
CLK+
OE/NC
1
2
3
(Top View)
6
5
4
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
NC/OE
GND
Pin #
1, 2
3
4
5
6
Descriptions
Selectable via ordering option
OE = Output enable; NC = No connect
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used
for CMOS.
VDD = Power supply
NVM
Control
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
OSC
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
1
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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1
Si540 Data Sheet • Ordering Guide
1. Ordering Guide
The Si540 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to access
this tool and for further ordering instructions.
XO Series
540
Description
Single Frequency
Temp Stability
A
B
C
Total Stability
2
±
20 ppm
±
10 ppm
±
7 ppm
±
50 ppm
±
25 ppm
±
20 ppm
A
B
C
Package
5x7 mm
3.2x5 mm
2.5x3.2 mm
G
Temperature Grade
-40 to 85 °C
540
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
A
A
A
-
-
-
-
-
-
-
A
B
G
R
Order
VDD Range
Option
2.5, 3.3 V
A
1.8, 2.5, 3.3 V
B
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
C
D
E
F
G
X
Device Revision
OE Pin
A
B
C
D
Pin 1
Pin 1
Pin 2
Pin 2
OE Polarity
Active High
Active Low
Active High
Active Low
R
<Blank>
Reel
Tape and Reel
Coil Tape
Frequency Code
3
Description
Mxxxxxx
F
CLK
< 1 MHz
xMxxxxx
1 MHz ≤ F
CLK
< 10 MHz
xxMxxxx
10 MHz ≤ F
CLK
< 100 MHz
xxxMxxx
100 MHz ≤ F
CLK
< 1000 MHz
1000 MHz ≤ F
CLK
≤ 1500 MHz
xxxxMxx
xxxxxx
Custom code if F
CLK
> 6 digits
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at
www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si540-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
2
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si540 Data Sheet • Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
Total Stability
1
F
STAB
Frequency stability Grade A
Frequency stability Grade B
Frequency stability Grade C
Rise/Fall Time
(20% to 80% V
PP
)
T
R
/T
F
LVPECL/LVDS/CML
CMOS / Dual CMOS
(C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE)
2
D
C
V
IH
V
IL
T
D
T
E
Powerup Time
Powerup VDD Ramp Rate
t
OSC
V
RAMP
Output Disable Time,
F
CLK
>10 MHz
Output Enable Time,
F
CLK
>10 MHz
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Fastest V
DD
ramp rate allowed on
startup
All formats
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
–10
–7
–50
–25
–20
—
—
—
45
0.7 × V
DD
—
—
—
—
—
Typ
—
—
—
—
3.3
2.5
1.8
100
75
80
74
80
64
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
—
Max
85
1500
400
250
3.465
2.625
1.89
145
111
125
108
125
100
20
10
7
50
25
20
350
1.5
550
55
—
0.3 × V
DD
3
20
10
9
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ppm
ppm
ppm
ppm
ppm
ps
ns
ps
%
V
V
µs
µs
ms
V/ms
3
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Si540 Data Sheet • Electrical Specifications
Parameter
LVPECL Output Option
3
Symbol
V
OC
V
O
Test Condition/Comment
Mid-level
Swing (diff)
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
Min
V
DD
– 1.42
1.1
1.125
0.8
0.6
0.5
660
–150
250
0.6
Typ
—
—
1.20
0.9
0.7
0.7
750
0
350
0.8
—
—
Max
V
DD
– 1.25
1.9
1.275
1.0
0.9
0.9
850
150
550
1.0
—
0.15 × V
DD
Unit
V
V
PP
V
V
V
PP
V
PP
mV
mV
mV
V
PP
V
V
LVDS Output Option
4
V
OC
V
O
Swing (F
CLK
≤ 1.4 GHz)
Swing (F
CLK
> 1.4 GHz)
HCSL Output Option
5
V
OH
V
OL
V
C
Output voltage high
Output voltage low
Crossing voltage
Swing (diff)
CML Output Option (AC-Coupled)
CMOS Output Option
V
O
V
OH
V
OL
I
OH
= 8/6/4 mA for 3.3/2.5/1.8V VDD 0.85 × V
DD
I
OL
= 8/6/4 mA for 3.3/2.5/1.8V VDD
—
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. NC (No Connect)
pins include a 50 kΩ pull-down to GND.
3. 50 Ω to V
DD
– 2.0 V.
4. R
term
= 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSNR
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Phase Jitter (RMS, 12kHz - 20MHz)
1
2.5 x 3.2 mm, 3.2 x 5 mm, F
CLK
≥ 100 MHz
Phase Jitter (RMS, 12kHz - 20MHz)
1
5 x 7 mm, F
CLK
≥ 100 MHz
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSNR
Symbol
ϕ
J
Test Condition/Comment
Differential Formats
CMOS, Dual CMOS
Differential Formats
CMOS, Dual CMOS
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
Min
—
—
—
—
—
—
—
—
Typ
125
200
150
200
-83
-83
-82
-85
Max
200
—
200
—
—
—
—
—
dBc
Unit
fs
fs
fs
fs
4
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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Si540 Data Sheet • Electrical Specifications
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical, 50ppm Total Stability Option)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
156.25 MHz LVDS
–110
–121
–132
–139
–151
–160
–161
156.25 MHz
LVPECL
–113
–123
–133
–139
–151
–162
–163
200 MHz LVDS
–107
–120
–130
–137
–149
–161
–162
200 MHz
LVPECL
–110
–120
–130
–137
–149
–166
–167
644.53125 MHz LVDS
–99
–109
–121
–127
–138
–155
–157
644.53125 MHz
LVPECL
–100
–110
–119
–127
–138
–156
–157
dBc/Hz
Unit
dBc/Hz
Unit
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at
www.silabs.com/oscillators.
Figure 2.1. Phase Jitter vs. Output Frequency
5
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.2 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • July 26, 2021
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