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72V283L7-5BC

Description
CABGA-100, Tray
Categorystorage    storage   
File Size446KB,46 Pages
ManufacturerIDT (Integrated Device Technology)
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72V283L7-5BC Overview

CABGA-100, Tray

72V283L7-5BC Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instructionLBGA, BGA100,10X10,40
Contacts100
Manufacturer packaging codeBC100
Reach Compliance Codenot_compliant
ECCN codeEAR99
Samacsys DescriptionCHIP ARRAY BGA 11.0 X 11.0 MM X 1.0 MM
Maximum access time5 ns
Other featuresIT CAN ALSO BE CONFIGURED AS 64K X 9; RETRANSMIT; ASYNCHRONOUS MODE IS ALSO POSSIBLE
Spare memory width9
Maximum clock frequency (fCLK)133.3 MHz
period time7.5 ns
JESD-30 codeS-PBGA-B100
JESD-609 codee0
length11 mm
memory density589824 bit
Memory IC TypeOTHER FIFO
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX18
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA100,10X10,40
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.5 mm
Maximum standby current0.015 A
Maximum slew rate0.035 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
width11 mm
Base Number Matches1
3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO
512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9
IDT72V223, IDT72V233
IDT72V243, IDT72V253
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9
IDT72V263, IDT72V273
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9
IDT72V283, IDT72V293
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
Choose among the following memory organizations:
IDT72V223
512 x 18/1,024 x 9
IDT72V233
1,024 x 18/2,048 x 9
IDT72V243
2,048 x 18/4,096 x 9
IDT72V253
4,096 x 18/8,192 x 9
IDT72V263
8,192 x 18/16,384 x 9
IDT72V273
16,384 x 18/32,768 x 9
IDT72V283
32,768 x 18/65,536 x 9
IDT72V293
65,536 x 18/131,072 x 9
Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
Up to 166 MHz Operation of the Clocks
User selectable Asynchronous read and/or write ports (BGA Only)
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Pin to Pin compatible to the higher density of IDT72V2103/72V2113
Big-Endian/Little-Endian user selectable byte representation
5V tolerant inputs
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
JTAG port, provided for Boundary Scan function (BGA Only)
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
*Available on the
BGA package only.
D
0
-D
n
(x9 or x18)
WEN
WCLK/WR
*
INPUT REGISTER
LD SEN
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
*
ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
512 x 18 or 1,024 x 9
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
FLAG
LOGIC
READ POINTER
BE
IP
IW
OW
MRS
PRS
TCK
*
TRST
*
TMS
**
TDI
*
TDO
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
RM
ASYR
*
RCLK/RD
JTAG CONTROL
(BOUNDARY SCAN)
*
OE
Q
0
-Q
n
(x9 or x18)
REN
*
4666 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2018
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2018
DSC-4666/18
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