NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6DQPCEC
Rev. 3, 11/2018
i.MX 6DualPlus/6QuadPlus
Applications Processors
Consumer Products
MCIMX6QP5Exx1AA
MCIMX6QP5Exx1AB
MCIMX6DP5Exx1AA
MCIMX6DP5Exx1AB
MCIMX6QP5Exx2AA
MCIMX6QP5Exx2AB
MCIMX6DP5Exx2AA
MCIMX6DP5Exx2AB
Package Information
FCPBGA Package
21 x 21 mm, 0.8 mm pitch
Ordering Information
See
Table 1
1
Introduction
1
The i.MX 6DualPlus/6QuadPlus processors offer the
highest levels of graphics processing performance in the
i.MX 6 series family and are ideally suited for graphics
intensive applications.
The i.MX 6DualPlus/6QuadPlus processors feature
advanced implementation of the quad
Arm
®
Cortex
®
-A9 core, which operates at speeds up to
1.2 GHz. They include updated versions of the 2D and
3D graphics processors, 1080p video processing, and
integrated power management. Each processor provides
a 64-bit DDR3/DDR3L/LPDDR2 memory interface and
a number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth
®
, GPS, hard drive, displays,
and camera sensors.
The i.MX 6DualPlus/6QuadPlus processors are
specifically useful for applications such as the
following:
• Graphics rendering for Human Machine
Interfaces (HMI)
• Video processing and display
2
3
4
5
6
7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 19
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Power Supplies Requirements and Restrictions . . 33
4.3 Integrated LDO Voltage Regulator Parameters . . 34
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 53
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 64
4.11 General-Purpose Media Interface (GPMI) Timing. 64
4.12 External Peripheral Interface Parameters . . . . . . . 73
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 138
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 138
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 139
Package Information and Contact Assignments . . . . . . 141
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 141
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 141
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Introduction
•
•
•
•
•
•
•
Netbooks (web tablets)
Nettops (Internet desktop devices)
High-end mobile Internet devices (MID)
High-end PDAs
High-end portable media players (PMP) with HD video capability
Gaming consoles
Portable navigation devices (PND)
The i.MX 6DualPlus/6QuadPlus processors offers numerous advanced features, such as:
• Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS needs of operating systems and games. The
Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing
the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio
decode.
• Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,
PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,
including eMMC up to rev 4.4/4.41.
• Smart speed technology—The processors have power management throughout the device that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
• Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
• Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, Neon
®
MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, 2 autonomous and independent image processing units (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: an OpenGL
®
ES 3.0 3D graphics accelerator with four shaders (up to 198 MTri/s
and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.
• Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces
(such as UART, I
2
C, and I
2
S serial audio, SATA-II, and PCIe-II).
• Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad
security reference manual (IMX6DQ6SDLSRM).
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
2
NXP Semiconductors
Introduction
•
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
1.1
Ordering Information
Table 1
shows examples of orderable part numbers covered by this data sheet. This table does not include
all possible orderable part numbers. The latest part numbers are available on
nxp.com/imx6series.
If your
desired part number is not listed in the table, or you have questions about available parts, see
nxp.com/imx6series
or contact your NXP representative.
Table 1. Example Orderable Part Numbers
Part Number
Quad/Dual
CPU Options
VPU, GPU
VPU, GPU
VPU, GPU
VPU, GPU
VPU, GPU
VPU, GPU
VPU, GPU
VPU, GPU
Speed
1
1 GHz
1 GHz
1 GHz
1 GHz
Temperature Grade
Extended commercial
Extended commercial
Extended commercial
Extended commercial
Package
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6DP5EYM1AA i.MX 6DualPlus
MCIMX6DP5EYM1AB i.MX 6DualPlus
MCIMX6QP5EYM1AA i.MX 6QuadPlus
MCIMX6QP5EYM1AB i.MX 6QuadPlus
MCIMX6DP5EVT2AA i.MX 6DualPlus
MCIMX6DP5EVT2AB i.MX 6DualPlus
MCIMX6QP5EVT2AA i.MX 6QuadPlus
MCIMX6QP5EVT2AB i.MX 6QuadPlus
1
1.2 GHz Extended commercial
1.2 GHz Extended commercial
1.2 GHz Extended commercial
1.2 GHz Extended commercial
For 1 GHz speed grade: If a 24 MHz clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz.
Figure 1
describes the part number nomenclature to identify the characteristics of the specific part number
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision).
Figure 1
applies to the i.MX 6DualPlus/6QuadPlus.
The two characteristics that identify which data sheet a specific part applies to are the part number series
field and the temperature grade (junction) field:
• The i.MX 6DualPlus/6QuadPlus Automotive Applications Processors data sheet (IMX6DQPAEC)
covers parts listed for the “Plus” series and with “A” indicating automotive temperature.
• The i.MX 6DualPlus/6QuadPlus Applications Processors for Consumer Products data sheet
(IMX6DQPCEC) covers parts listed with “D (Commercial temp)” or “E (Extended Commercial
temp)”
• The i.MX 6DualPlus/6QuadPlus Applications Processors for Industrial Products data sheet
(IMX6DQPIEC) covers parts listed with “C (Industrial temp)”
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors
3
Introduction
Ensure that you have the right data sheet for your specific part by checking the fields: Part # Series
(DP/QP), temperature grade (junction) (A), and Frequency (8).
MC
Qualification level
Prototype Samples
Mass Production
Special
IMX6
MC
PC
MC
SC
XX
@
+
VV
$
%
A
Silicon revision
Rev 1.0
Rev 1.1
A
A
B
Fusing
Real Codec off and no HDCP or DTCP
%
A
Part # series
i.MX 6QuadPlus
i.MX 6DualPlus
XX
QP
DP
Frequency
800 MHz
1
(Industrial grade)
852 MHz (Automotive grade)
$
8
8
1
2
RoHS
Part differentiator
Industrial with VPU, GPU, no MLB
Automotive with VPU, GPU
Consumer, with VPU, GPU
Automotive with GPU, no VPU
@
7
6
5
4
1 GHz
2
1.2 GHz
Package type
Temperature Tj
Extended commercial: -20 to + 105
°
C
Industrial: -40 to +105
°
C
Automotive: -40 to + 125
°
C
+
E
C
A
FCPBGA 21x21 0.8mm (lidded)
FCPBGA 21x21 0.8mm (non lidded)
VT
YM
1. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Figure 1. Part Number Nomenclature—i.MX 6DualPlus and i.MX 6QuadPlus
1.2
Features
The i.MX 6DualPlus/6QuadPlus processors are based on Arm Cortex-A9 MPCore platform, which has
the following features:
• Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone
®
)
• The core configuration is symmetric, where each core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The Arm Cortex-A9 MPCore complex includes:
• General Interrupt Controller (GIC) with 128 interrupt support
• Global Timer
• Snoop Control Unit (SCU)
• 1 MB unified I/D L2 cache, shared by two/four cores
• Two Master AXI (64-bit) bus interfaces output of L2 cache
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
4
NXP Semiconductors
Introduction
•
•
Frequency of the core (including Neon and L1 cache) as per
Table 6.
NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
• Boot ROM, including HAB (96 KB)
• Internal multimedia / shared, fast access RAM (OCRAM, 512 KB)
• Secure/non-secure RAM (16 KB)
• External memory interfaces:
— 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels,
supporting DDR interleaving mode, for dual x32 LPDDR2
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
— 16/32-bit PSRAM, Cellular RAM
Each i.MX 6DualPlus/6QuadPlus processor enables the following interfaces to external devices (some of
them are muxed and not available simultaneously):
• Hard Disk Drives—SATA II, 3.0 Gbps
• Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.
— One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
HD1080 and WXGA at 60 Hz)
— LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two
ports up to 85 MP/sec each
— HDMI 1.4 port
— MIPI/DSI, two lanes at 1 Gbps
• Camera sensors:
— Parallel Camera port (up to 20 bit and up to 240 MHz peak)
— MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to
800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to
four data lanes. Each i.MX 6DualPlus/6QuadPlus processor has four lanes.
• Expansion cards:
— Four MMC/SD/SDIO card ports all supporting:
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors
5
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