March 1998
FDN357N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT
TM
-3 N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very high
density process is especially tailored to minimize on-state
resistance. These devices are particularly suited for low voltage
applications in notebook computers, portable phones, PCMCIA
cards, and
other battery powered circuits where fast
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
1.9 A, 30 V, R
DS(ON)
= 0.090
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.060
Ω
@ V
GS
= 10 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT
TM
-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOT -6
TM
SuperSOT -8
TM
SO-8
SOT-223
SOIC-16
D
D
7
35
S
SuperSOT -3
TM
G
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
,T
STG
R
θ
JA
R
θ
JC
Parameter
Drain-Source Voltage
T
A
= 25
o
C unless other wise noted
FDN357N
30
±20
1.9
10
(Note 1a)
(Note 1b)
Units
V
V
A
Gate-Source Voltage - Continuous
Drain/Output Current - Continuous
- Pulsed
Maximum Power Dissipation
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDN357N Rev.C
Electrical Characteristics
(T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25
o
C
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55°C
I
GSSF
I
GSSR
V
GS(th)
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
(Note)
30
36
1
10
100
-100
V
mV/
o
C
µA
µA
nA
nA
∆
BV
DSS
/
∆
T
J
I
DSS
V
GS
= 20 V,V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25 C
V
GS
= 4.5 V, I
D
= 1.9 A
T
J
=125°C
V
GS
= 10 V, I
D
= 2.2 A
o
ON CHARACTERISTICS
Gate Threshold Voltage
Gate Threshold Voltage Temp. Coefficient
Static Drain-Source On-Resistance
1
1.6
-3.6
0.081
0.11
0.053
2
V
mV/
o
C
∆
V
GS(th)
/
∆
T
J
R
DS(ON)
0.09
0.14
0.06
Ω
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Note:
On-State Drain Current
Forward Transconductance
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 5 V, I
D
= 1.9 A
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
5
5
A
S
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note)
235
145
50
pF
pF
pF
SWITCHING CHARACTERISTICS
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
Ω
5
12
12
3
10
22
22
8
5.9
ns
ns
ns
ns
nC
nC
nC
V
DS
= 10 V, I
D
= 1.9 A,
V
GS
= 5 V
4.2
1.3
1.7
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 0.42 A
(Note)
0.42
0.71
1.2
A
V
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment :
a. 250
o
C/W when mounted on
a 0.02 in
2
pad of 2oz Cu.
b. 270
o
C/W when mounted on
a 0.001 in
2
pad of 2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDN357N Rev.C
Typical Electrical Characteristics
10
I
D
, DRAIN-SOURCE CURRENT (A)
1.8
DRAIN-SOURCE ON-RESISTANCE
1.6
1.4
1.2
1
0.8
0.6
0.4
V
GS
= 10V
6.0
5.0
4.5
R
DS(ON)
, NORMALIZED
8
4.0
V
GS
=3.5V
6
4.0
4.5
5.0
6.0
7.0
10
3.5
4
2
3.0
0
0
0.5
1
1.5
2
2.5
3
0
2
4
6
8
10
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate
R
DS(ON)
, DRAIN-SOURCE ON-RESISTANCE
1.6
DRAIN-SOURCE ON-RESISTANCE
0.25
I
D
= 1.9A
1.4
I
D
=0.95A
0.2
V
GS
= 4.5V
R
DS(ON)
, NORMALIZED
1.2
0.15
1
0.1
T = 125°C
A
T = 25°C
A
0.8
0.05
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
0
2
4
6
8
10
V
GS
,GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
14
12
I
D
, DRAIN CURRENT (A)
10
8
6
4
2
0
25°C
125°C
I
S
, REVERSE DRAIN CURRENT (A)
V
DS
= 10V
T
A
= -55°C
10
V
GS
= 0V
1
TJ = 125°C
25°C
-55°C
0.1
0.01
0.001
1
2
3
4
5
6
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDN357N Rev.C
Typical Electrical And Thermal Characteristics
10
V
GS
, GATE-SOURCE VOLTAGE (V)
600
I
D
= 1.9A
8
CAPACITANCE (pF)
V
DS
= 5V
10V
15V
300
200
C
iss
Coss
6
100
4
50
2
20
0.1
f = 1 MHz
V
GS
= 0 V
0.2
0.5
1
2
5
10
C
rss
0
30
0
2
4
Q
g
, GATE CHARGE (nC)
6
8
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
20
10
I
D
, DRAIN CURRENT (A)
5
N)
(O
DS
R
IT
LIM
50
1m
s
10m
40
s
POWER (W)
30
SINGLE PULSE
R
θ
JA
=250° C/W
T
A
= 25°C
1
0.5
100
1s
10s
ms
20
0.1
0.05
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 250°C/W
T
A
= 25°C
A
0.2
0.5
1
2
DC
10
0.01
0.1
0
0.0001
5
10
20
50
0.001
0.01
0.1
1
10
100 300
SINGLE PULSE TIME (SEC)
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
P(pk)
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 250 °C/W
t
1
t
2
T
J
- T
A
= P * R
θ
JA (t)
Duty Cycle, D = t
1
/t
2
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
300
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1a.
Transient thermal response will change depending on the circuit board design.
FDN357N Rev.C
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