93LC46/56/66
1K/2K/4K 2.0V CMOS Serial EEPROM
FEATURES
• Single supply with programming operation down
to 2.0V (Commercial only)
• Low power CMOS technology
- 1 mA active current typical
- 5
µ
A standby current (typical) at 3.0V
• ORG pin selectable memory configuration
- 128 x 8 or 64 x 16 bit organization (93LC46)
- 256 x 8 or 128 x 16 bit organization (93LC56)
- 512 x 8 or 256 x 16 bit organization (93LC66)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed
on 93LC56 and 93LC66
• 1,000,000 E/W cycles guaranteed on 93LC46*
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
• Available for extended temperature ranges:
- Commercial: 0˚Cto +70˚C
- Industrial: -40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 93LC46/56/66 are 1K,
2K and 4K low voltage serial Electrically Erasable
PROMs. The device memory is configured as x8 or
x16 bits depending on the ORG pin setup. Advanced
CMOS technology makes these devices ideal for low
power non-volatile memory applications. The 93LC
Series is available in standard 8-pin DIP and 8/14-pin
surface mount SOIC packages. The 93LC46X/56X/
66X are offered in “SN” package only.
BLOCK DIAGRAM
V
CC
V
SS
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DATA REGISTER
DI
MODE
DECODE
LOGIC
OUTPUT
BUFFER
DO
CS
CLK
CLOCK
GENERATOR
PACKAGE TYPE
SOIC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
NC
Vcc
NU
NC
ORG
Vss
NC
DIP
SOIC
SOIC
CS
CLK
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NU
ORG
V
SS
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NU
ORG
V
SS
NU
Vcc
CS
CLK
1
2
3
4
8
7
6
5
ORG
Vss
DO
DI
NC
DI
DO
NC
93LC46
93LC56
93LC66
93LC46
93LC56
93LC66
93LC46X
93LC56X
93LC66X
93LC56
93LC66
**Future: 10,000,000 E/W cycles guaranteed
©
1995 Microchip Technology Inc.
DS11168I-page 1
93LC46/56/66
1.0
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Name
CS
CLK
DI
DO
V
SS
ORG
NU
NC
V
CC
PIN FUNCTION TABLE
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Not Utilized
No Connect
Power Supply
Maximum Ratings*
Vcc ........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
.... -0.6V to Vcc +1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
Commercial Vcc = +2.0V to +6.0V
Industrial
Vcc = +2.5V to +6.0V
(C): Tamb = 0˚C to +70˚C
(I): Tamb = -40˚C to +85˚C
Units
V
V
V
V
V
V
V
V
µ
A
µ
A
pF
mA
mA
µ
A
µ
A
µ
A
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
Conditions
V
CC
≥
2.7V
V
CC
< 2.7V
V
CC
≥
2.7V
V
CC
< 2.7V
I
OL
= 2.1 mA; Vcc = 4.5V
I
OL
=100
µ
A; Vcc = Vcc Min.
I
OH
= -400
µ
A; Vcc = 4.5V
I
OH
= -100
µ
A; Vcc = Vcc Min.
V
IN
= 0.1V to Vcc
V
OUT
= 0.1V to Vcc
V
IN
/V
OUT
= 0 V (Note 1 & 3)
Tamb = +25˚C, F
CLK
= 1 MHz
F
CLK
= 2 MHz; Vcc = 6.0V (Note 3)
F
CLK
= 2 MHz; Vcc = 6.0V
F
CLK
= 1 MHz; Vcc = 3.0V
CLK = CS = 0V; Vcc = 6.0V
CLK = CS = 0V; Vcc = 3.0V
Vcc
≥
4.5V
Vcc < 4.5V
Parameter
High level input voltage
Low level input voltage
Low level output voltage
High level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Symbol
V
IH1
V
IH2
V
IL1
V
IL2
V
OL1
V
OL2
V
OH1
V
OH2
I
LI
I
LO
C
IN
, C
OUT
I
CC
write
I
CC
read
Min.
2.0
0.7 Vcc
-0.3
-0.3
—
—
2.4
Vcc-0.2
-10
-10
—
—
—
Max.
Vcc +1
Vcc +1
0.8
0.2 Vcc
0.4
0.2
—
—
10
10
7
3
1
500
Standby current
I
CCS
—
100
30
Clock frequency
F
CLK
—
2
1
Clock high time
T
CKH
250
—
Clock low time
T
CKL
250
—
Chip select setup time
T
CSS
50
—
Chip select hold time
T
CSH
0
—
Chip select low time
T
CSL
250
—
Data input setup time
T
DIS
100
—
Data input hold time
T
DIH
100
—
Data output delay time
T
PD
—
400
Data output disable time
T
CZ
—
100
Status valid time
T
SV
—
500
Program cycle time
T
WC
—
10
T
EC
—
15
T
WL
—
30
Note 1: This parameter is tested at Tamb = 25˚C and F
CLK
= 1 MHz.
Note 2: Typical program cycle time is 4 ms per word.
Note 3: This parameter is periodically sampled and not 100% tested.
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
C
L
= 100 pF
C
L
= 100 pF (Note 3)
C
L
= 100 pF
ERASE/WRITE mode (Note 2)
ERAL mode
WRAL mode
DS11168I-page 2
©
1995 Microchip Technology Inc.
93LC46/56/66
TABLE 1-3:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC46: ORG = 1 (X 16 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
A5 A4 A3 A2 A1 A0
1 1 X X X X
A5 A4 A3 A2 A1 A0
1 0 X X X X
A5 A4 A3 A2 A1 A0
0 1 X X X X
0 0 X X X X
Data In
—
—
—
—
D15 - D0
D15 - D0
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
25
9
9
9
25
25
9
TABLE 1-4:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC46: ORG = 0 (X 8 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X
A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X
A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X
0 0 X X X X X
Data In
—
—
—
—
D7 - D0
D7 - D0
—
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
18
10
10
10
18
18
10
TABLE 1-5:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC56: ORG = 1 (X 16 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
X A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X
X A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X
X A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X
0 0 X X X X X X
Data In
—
—
—
—
D15 - D0
D15 - D0
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
27
11
11
11
27
27
11
TABLE 1-6:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC56: ORG = 0 (X 8 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
X A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X
X A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X
X A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X
0 0 X X X X X X X
Data In
—
—
—
—
D7 - D0
D7 - D0
—
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
20
12
12
12
20
20
12
TABLE 1-7:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC66: ORG = 1 (X 16 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X
A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X
A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X
0 0 X X X X X X
Data In
—
—
—
—
D15 - D0
D15 - D0
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
27
11
11
11
27
27
11
TABLE 1-8:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC66: ORG = 0 (X 8 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X
A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X
A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X
0 0 X X X X X X X
Data In
—
—
—
—
D7 - D0
D7 - D0
—
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
20
12
12
12
20
20
12
©
1995 Microchip Technology Inc.
DS11168I-page 3
93LC46/56/66
2.0
FUNCTIONAL DESCRIPTION
3.0
READ
When the ORG pin is connected to Vcc, the (x16) orga-
nization is selected. When it is connected to ground,
the (x8) organization is selected.
Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is nor-
mally held in a high-Z state except when reading data
from the device, or when checking the READY/BUSY
status during a programming operation. The ready/
busy status can be verified during an Erase/Write oper-
ation by polling the DO pin; DO low indicates that pro-
gramming is still in progress, while DO high indicates
the device is ready. The DO will enter the high-Z state
on the falling edge of the CS.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) or 8 bit
(x8 organization) output string. The output data bits will
toggle on the rising edge of the CLK and are stable
after the specified time delay (T
PD
). Sequential read is
possible when CS is held high. The memory data will
automatically cycle to the next register and output
sequentially.
4.0
ERASE/WRITE ENABLE AND
DISABLE
2.1
START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
The 93LC46/56/66 powers up in the Erase/Write Dis-
able (EWDS) state. All programming modes must be
preceded by an Erase/Write Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed, pro-
gramming remains enabled until an EWDS instruction
is executed or Vcc is removed from the device. To pro-
tect against accidental data disturb, the EWDS instruc-
tion can be used to disable all Erase/Write functions
and should follow all programming operations. Execu-
tion of a READ instruction is independent of both the
EWEN and EWDS instructions.
5.0
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical "0" indicates that program-
ming is still in progress. DO at logical "1" indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word (Typical).
2.2
DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
6.0
WRITE
2.3
Data Protection
The WRITE instruction is followed by 16 bits (or by 8
bits) of data which are written into the specified
address. After the last data bit is put on the DI pin, CS
must be brought low before the next rising edge of the
CLK clock. This falling edge of CS initiates the self-
timed auto-erase and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is com-
plete. DO at logical "0" indicates that programming is
still in progress. DO at logical "1" indicates that the reg-
ister at the specified address has been written with the
data specified and the device is ready for another
instruction.
The WRITE cycle takes 4 ms per word (Typical).
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
DS11168I-page 4
©
1995 Microchip Technology Inc.
93LC46/56/66
7.0
ERASE ALL
The ERAL instruction will erase the entire memory
array to the logical "1" state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The ERAL instruction is guar-
anteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is com-
plete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
and clock LOW time (T
CKL
). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't
care inputs waiting for a new start condition to be
detected.
Note:
CS must go LOW between consecutive
instructions.
8.0
WRITE ALL
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin
is not necessary after the device has entered the self
clocking mode. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status. The WRAL
instruction is guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
The WRAL cycle takes 30 ms maximum (16 ms typi-
cal).
9.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
9.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
PD
after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (T
CSL
) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
9.0
9.1
PIN DESCRIPTION
Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the
CS input signal. If CS is brought LOW during a pro-
gram cycle, the device will go into standby mode as
soon as the programming cycle is completed.
CS must be LOW for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
9.5
Organization (ORG)
9.2
Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LCXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (T
CKH
)
When ORG is connected to Vcc or floated, the (x16)
memory organization is selected. When ORG is tied to
V
SS
, the (x8) memory organization is selected. ORG
can only be floated for clock speeds of 1 MHz or less
for the (X16) memory organization. For clock speeds
greater than 1 MHz, ORG must be tied to Vcc or V
SS
.
©
1995 Microchip Technology Inc.
DS11168I-page 5
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