1Mx8, 20 - 45ns, STACK/DIP
30A129-12
B
8 Megabit High Speed CMOS SRAM
DPS1MX8MKN3
DESCRIPTION:
The DPS1MX8MKN3 High Speed SRAM ‘’STACK’’
devices are a revolutionary new memory subsystem
using Dense-Pac Microsystems’ ceramic Stackable
Leadless Chip Carriers (SLCC) mounted on a co-fired
ceramic substrate having side-brazed leads.
The
device packs 8-Megabits of low-power CMOS static
RAM in a 600-mil-wide, 32-pin dual-in-line package.
The DPS1MX8MKN3 STACK devices contain two
512K x 8 SRAM die, each packaged in a hermetically
sealed SLCC, making the devices suitable for
commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of devices offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
•
Organizations Available:
1Meg x 8
•
Access Times:
20*, 25, 30, 35, 45ns
•
Fully Static Operation
- No clock or refresh required
•
Single +5V Power Supply,
±
10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Low Data Retention Voltage:
2.0V min.
•
Package Available:
32 Pin DIP
*
Commercial and Industrial Grade only.
PIN-OUT DIAGRAM
PIN NAMES
A0 - A18
I/O0 - I/O7
CE0, CE1
WE
V
DD
V
SS
Address Inputs
Data Input/Output
Low Chip Enables
Write Enable
Power (+5V)
Ground
30A129-12
REV. B
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS1MX8MKN3
TRUTH TABLE
Mode
Not Selected
Read
Write
H = HIGH
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
Supply
Current
Standby
Active
Active
X = Don’t Care
3
CE
H
L
L
WE
X
H
L
L = LOW
I/O Pin
High-Z
D
OUT
D
IN
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
2
V
IL
Input LOW Voltage -0.5
0.8
V
M/B -55 +25 +125
Operating
o
T
A
I
-40 +25
+85
C
Temperature
C
0 +25
+70
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
3
Parameter
Value
Unit
Storage Temperature
-65 to +150
°C
Temperature Under Bias
-55 to +125
°C
Supply Voltage
1
-0.5 to +7.0
°C
1
Input/Output Voltage
-0.5 to V
DD
+0.5 V
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
CAPACITANCE
4
:
TA = 25°C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Data Input/Output
Max.
18
12
18
22
Unit
pF
Condition
V
IN2
= 0V
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ
, t
HZ
, and t
WHZ
t
LZ
, t
HZ
, and t
WHZ
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4 V
D
OUT
C
L
*
255Ω
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
Typ.
(†)
-
-
145
2
40
300
200
-
-
2.4
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
-10
-20
+10
+20
230
20
120
1000
600
0.4
-10
-20
+10
+20
240
20
120
2000
1600
0.4
-10
-20
+10
+20
240
30
120
4000
3600
0.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
2
30A129-12
REV. B
Dense-Pac Microsystems, Inc.
DPS1MX8MKN3
Data Retention AC Characteristics
8
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
t
RC
t
AA
t
CO
t
LZ
t
HZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
CE to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
20
20
20
3
8
4
25
25
25
3
10
5
30
30
30
3
15
5
35
35
35
3
20
5
45
45
45
3
25
5
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
:
Over operating ranges
No. Symbol
7
8
9
10
11
12
13
14
15
16
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
13
13
0
13
0
0
9
0
3
8
25
15
15
0
15
0
0
10
0
3
10
30
20
20
0
20
0
0
12
0
3
12
35
25
25
0
25
0
0
15
0
3
15
45
35
35
0
35
0
0
20
0
3
20
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
30A129-12
REV. B
3
DPS1MX8MKN3
Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A129-12
REV. B
Dense-Pac Microsystems, Inc.
DPS1MX8MKN3
WRITE CYCLE 2:
WE Controlled.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1.
All voltages are with respect to V
SS
.
2.
-2.0V min. for pulse width less than 20ns (V
IL
min. = -0.5V
at DC level).
3.
Stresses greater than those under
ABSOLUTE MAXIMUM
RATINGS
may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
4.
This parameter is guaranteed and not 100% tested.
5.
Transition is measured at the point of
±500mV
from steady
state voltage.
6.
When CE is LOW and WE is HIGH, I/O pins are in the
output state,and input signals of opposite phase to the
outputs must not be applied.
7. The outputs are in a high impedance state when WE is
LOW.
8.
CE and WE can initiate and terminate WRITE Cycle.
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A129-12
REV. B
5
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