PACS1284
IEEE 1284 ECP/EPP Termination Network
Features
•
•
•
•
•
•
•
Single chip IEEE 1284 parallel port termination
28-pin QSOP package, smallest physical
solution
17 terminating lines in a single package
In-system ESD protection to
±
8KV, HBM
In-system ESD protection to
±
4KV per
IEC 61000-4-2
Protects downstream devices to 30V
Lead-free version available
Product Description
California Micro Devices’ PACS1284 Parallel Port Ter-
mination Network provides a complete integrated solu-
tion for the entire IEEE 1284 interface in a single
QSOP package.
To support the bi-directional transfer data rates of
enhanced high-speed parallel ports, the IEEE 1284
Standard recommends a combined termination/pull-up
filter network between the driver/receiver and the cable
at both ends of the parallel port interface. In addition,
government EMC compatibility requirements impose
strict filtering requirements on the parallel port. The
California Micro Devices PACS1284 addresses all
these requirements by providing a seventeen-line IEEE
1284-compliant network in a thin film integrated circuit.
The device provides a complete parallel port termina-
tion solution for space critical applications by integrat-
ing a total of 60 discrete components. In addition, all
the I/O pins are ESD protected for contact discharges
up to
±
4KV per the Human Body Model (HBM), with the
output pins having the highest probability of ESD pulse
exposure protected to
±
8KV (HBM), thereby providing
the necessary robustness for the port’s application
environment.
The PACS1284 is manufactured in a 28-pin QSOP
package and is available with optional lead-free finish-
ing.
Applications
•
•
•
•
ECP/EPP Parallel Port termination
PC Peripherals
Notebook and Desktop computers
Engineering Workstations and Servers
Electrical Schematic
PACS1284-02:
R1 = 2.2kΩ
R2 = 33Ω
R3 = 2.2kΩ
C = 220pF
PACS1284-04:
R1 = 4.7kΩ
R2 = 33Ω
R3 = 4.7kΩ
C = 180pF
28
27
26
25
24
23
22 21
20
19
18
17
16
15
R1
R3
R1
R1
R1
R2
R1
R2
R1
R2
R1
R2
R1
R2
R3
R1
R2
R3
R1
R2
R3
R1
R2
R1
R2
R3
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
1
PACS1284
PACKAGE / PINOUT DIAGRAM
CAP-FILTERED; R1 PULL-UP
CAP-FILTERED; R1 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
SUPERCHIP SIDE SERIES-TERMINATED
SUPERCHIP SIDE SERIES-TERMINATED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CAP-FILTERED; R3 PULL-UP
CAP-FILTERED; R1 PULL-UP
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
GND
CONNECTOR SIDE SERIES-TERMINATED
V
CC
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CONNECTOR SIDE SERIES-TERMINATED
CAP-FILTERED; R3 PULL-UP
Note: This drawing is not to scale.
28-pin QSOP
PIN DESCRIPTIONS
PINS
1, 2, 27
8, 10, 12,
15, 28
3-7,
9,11,
13,14
16-19,
21,
23-26
20
22
PIN NAME
Cap-filtered;
R1 Pull-up
Cap-filtered;
R3 Pull-up
SuperChip Side
Series-terminated
Connector Side
Series-terminated
V
CC
GND
DESCRIPTION
IEEE 1284 signals which require no series termination; pull-up is R1 value.
IEEE 1284 signals which require no series termination; pull-up is R3 value.
IEEE 1284 signals on the Super I/O Chip side which require series termination.
IEEE 1284 signals on the Parallel Port Connector side which require series termination.
Supply rail for the device
Ground reference for the device
Ordering Information
STANDARD VALUES
Product
PACS1284-02
PACS1284-04
R1 (Ω)
2.2k
4.7k
R2 (Ω)
33
33
R3 (Ω)
2.2k
4.7k
C (pF)
220
180
PART NUMBERING INFORMATION
Standard FInish
Ordering Part
Pins
28
28
Package
QSOP
QSOP
Number
1
PACS1284-02Q
PACS1284-04Q
Part Marking
PACS128402Q
PACS128404Q
Lead-free Finish
Ordering Part
Number
1
PACS1284-02QR
PACS1284-04QR
Part Marking
PACS128402QR
PACS128404QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
06/07/04
PACS1284
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
V
CC
Voltage
Input Voltage Range, no clamping
Storage Temperature Range
Power Dissipation per Resistor
Package Power Dissipation
RATING
6.0
-6.0 to 6.0
-65 to +150
100
1.00
UNITS
V
V
°C
mW
W
STANDARD OPERATING CONDITIONS
PARAMETER
V
CC
Voltage
Operating Temperature
RATING
5.0
0 to +70
UNITS
V
°C
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
TOL
R
TOL
C
I
LEAK
V
ESD
PARAMETER
Absolute Resistance Tolerance
(R1, R2, R3)
Absolute Capacitance Tolerance
Leakage current to GND
CONDITIONS
Measured at T
A
=25°C
Measured at 1MHz, 2.5VDC, T
A
=25°C
Measured at 5.0VDC, T
A
=25°C
±4
MIN
TYP
MAX
±10
±20
1
UNITS
%
%
µA
kV
Peak Discharge Voltage at any I/O Per MIL-STD-883, Method 3015
(HBM); C
Discharge
=100pF;
R
Discharge
=1.5KΩ; Notes 2,3
In-System ESD Protection
Per MIL-STD-883, Method 3015
(HBM); C
Discharge
=100pF;
R
Discharge
=1.5KΩ; Notes 2,3
Per IEC 61000-4-2 Level 2;
C
Discharge
=150pF; R
Discharge
=330Ω;
Notes 2,3
ESD applied to connector pin, mea-
sured at corresponding input pin; +8kV
discharge, Human Body Model
Note 2
V
ESD
±8
kV
V
ESD
In-System ESD Protection
±4
kV
V
CL
Clamping voltage under ESD
discharge
±30
V
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
Note 2: Guaranteed by design.
Note 3: ESD contact discharge between pin 22 (GND) and pins 1, 2, 8, 10, 12, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, & 28 (one
at a time, all other I/O pins open),
pin 20=5V; pin 22=GND
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
3
PACS1284
Performance Information
Filter Capacitors
Figure 1
shows typical insertion loss graphs for the
PACS1284, for Data and Strobe signals. The curves
are dependent on the physical location of the filter ele-
ments with respect to the ground and V
CC
terminals of
the device.
These graphs are measured in a 50 Ohm environment.
The signal is introduced at the series resistor input and
the output is measured at the corresponding filter
capacitor.
The three plotted lines in
Figure 1
depict the following
measurements:
• Line labeled "A" is measured between pin 14
(input) and pin 16 (output).
• Line labeled "B" is measured between pin 3 (input)
and pin 26 (output).
• Line labeled "C" is measured between pin 6 (input)
and pin 23 (output).
The "A" graph depicts “worst case” filter performance,
while "C" represents a “best case” situation. Graphs of
all other filter elements will fall between these two. (The
filter insertion loss was measured using a Hewlett
Packard HP8753C Analyzer.)
S
12
S
21
in dB
0
-10
A
-20
B
-30
C
-40
-50
300
450
600
750
900
1050
1200
(FREQUENCY, MHz)
Figure 1. Typical Filter Insertion Loss for PACS1284 (S
21
in dB, T
A
=25°C)
© 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
06/07/04
PACS1284
Application Information
Termination Considerations
The IEEE 1284 specification requires both termination
and EMI filtering on a total of 17 signal lines. Control
and Status lines (8 in total) only require a pull-up resis-
tor and a filter capacitor. The Data lines and Strobe
also require a series termination resistor in addition to
the pull-up resistors and filter capacitors. See
Table 1,
in conjunction with the schematic diagram on page 1.
Table 1: IEEE 1284 Termination Requirements
Interfacing to IEEE 1284 Connectors
IEEE 1284 defines three interface connectors:
• 1284 A is a 25-pin DB series connector which is
the de facto PC standard for the host connection.
• 1284 B is a 36-pin, 0.085 inch centerline connector
used on the peripheral device.
• 1284 C is a new 36-pin, 0.050 inch centerline con-
nector which can be used for both host and periph-
eral.
Figure 2A
shows a possible hook-up between
1284-A connector on a PC motherboard and
PACS1284, illustrating how the pin configuration of
PACS1284 allows for easy interconnect between
two. The dotted I/O signals of the PACS1284
typically be connected to a Super I/O chip on
motherboard.
the
the
the
the
will
the
SIGNAL TERMINATION REQUIREMENTS
Signal Name
Data1 - Data8
Strobe
Init
AutoFeedXT
Selectin
ACK
Busy
Paper Empty
Select
Fault
Series Termination
Yes
Yes
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Not Required
Figure 2B
shows a possible hook-up between the
1284-B connector on a peripheral and the PACS1284.
Figure 2C
shows a possible hook-up between the
1284-C connector and the PACS1284.
Figure 2A:
1284-A Connector
Host
14
25
19
1
Figure 2B:
1284-B Connector
Peripheral
36
19
13
1
18
1
2
20
Figure 2C:
1284-C Connector
Host/Peripheral
36
18
PACS1284
SUPER 1284
1
PACS1284
SUPER 1284
PACS1284
SUPER 1284
= GND
= V
CC
= FLOW
THROUGH
SIGNALS
1
= GND
= V
CC
1
Figure 2. Example Connections of IEEE 1284 Connectors with PACS1284
© 2004 California Micro Devices Corp. All rights reserved.
06/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲
Tel: 408.263.3214
▲
Fax: 408.263.7846
▲
www.calmicro.com
5
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