PACDN007Q datasheet, PDF - EEWORLD Datasheet

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PACDN007Q: DescriptionUNIDIRECTIONAL, 36 ELEMENT, SILICON, TVS DIODE; Categorysemiconductor Discrete semiconductor; File Size108KB，3 Pages; ManufacturerCALMIRCO; Websitehttp://www.calmicro.com/

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PACDN007Q Overview

UNIDIRECTIONAL, 36 ELEMENT, SILICON, TVS DIODE

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CALIFORNIA MICRO DEVICES

PAC DN007

Applications

Parallel printer port protection

ESD protection for sensitive

electronic equipment.

18 CHANNEL ESD PROTECTION ARRAY

Features

18-channel ESD protection

15KV ESD protection (HBM)

15KV contact discharge ESD protection

per IEC 61000-4-2

Low loading capacitance, 7 pF typ.

24-pin QSOP package

Product Description

The PAC DN007 is a diode array designed to provide 18 channels of ESD protection for electronic components or

sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V

) or

negative (V

) supply. The PAC DN007 will protect against ESD pulses up to 15 KV Human Body Model, and 15KV

contact discharge per International Standard IEC 61000-4-2.

This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low

loading capacitance for all signal lines.

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC CONFIGURATION

Diode Forward DC Current

(Note 1)

40mA

Storage Temperature

-65 C to 150

Operating Temperature Range

-20°C to 85°C

DC Voltage at any Channel Input V

-0.5V to V

+0.5V

Note 1: Only one diode conducting at a time.

STANDARD SPECIFICATIONS

Parameter

Min.

Operating Supply Voltage ( V

- V

)

Supply Current, ( V

- V

) = 5 .5 V, T = 25°C

0.65 V

D iode Forward Voltage, I

= 20mA, T = 25°C

ESD Protection

Peak D ischarge Voltage at any Channel Input, in-system

(Note 2)

000

Human Body Model, Method 3015

(Note 3, 4)

±15 KV

000

Contact D ischarge per IEC 61000-4-2

(Note 5)

Channel Clamp Voltage @ 15KV ESD HBM, T = 25°C

000

Positive transients

000

Negative transients

Channel Leakage Current, T = 25°C

Channel Input Capacitance (Measured @ 1 MHz)

= 5V, V

= 0V, V

= 2 .5 V

(Note 4)

Package Power Rating

Note

Typ.

Max.

5.5 V

10 µ A

0.95 V

(Notes 3, 4)

±0.1 µA

7pF

+ 13.0 V

- 13.0 V

±1.0 µA

1 2 pF

1.0W

From I/O pins to V

or V

only. V

bypassed to V

with 0.2

µF

ceramic capacitor.

Human Body Model per MIL-STD-883, Method 3015, C

Discharge

=100pF, R

Discharge

=1.5K

Ω

, V

=5.0V, V

=GND.

This parameter is guaranteed by characterization.

Standard IEC 61000-4-2 with C

Discharge

=150pF, and R

Discharge

=330

Ω

, V

=5V, V

=GND.

is a registered trademark and PAC is a trademark of California Micro Devices.

11/98

C0290498D

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

CALIFORNIA MICRO DEVICES

PAC DN007

Similarly for negative ESD pulses, parasitic series inductance from the V

pin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies

exhibit a much higher output impedance to fast transient current spikes. In the V

equation above, the V

Supply

term, in

reality, is given by (V

+ I

esd

x R

out

), where V

and R

out

are the nominal supply DC output voltage and effective output

impedance of the power supply respectively. As an example, a R

out

of 1 ohm would result in a 10V increment in V

for a

peak I

esd

of 10A.

To mitigate these effects, a high frequency bypass capacitor should be connected between the V

pin of the ESD Protection

Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge

transferred by the ESD pulse with minimal change in V

. Typically a value in the 0.1 µF to 0.2 µF range is adequate for

IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be

increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this

application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,

connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance

inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply

voltage.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V

pin of the

Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray

series inductance.

11/98

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

PACDN007Q Related Products

	PACDN007Q	PACDN007
Description	UNIDIRECTIONAL, 36 ELEMENT, SILICON, TVS DIODE	UNIDIRECTIONAL, 36 ELEMENT, SILICON, TVS DIODE

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