Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also subject
to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in this datasheet
for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration should be performed
after initial turn-on and the device reaches thermal stability. (4) Although many hundreds of thousands of filter configurations are available using
ispPAC80, not every type will have corner frequencies available from exactly 50kHz to 500kHz, depending on the tables available from within PAC-
Designer filter design tools. The general specifications given under this heading are realized using the Elliptic filter types. (5) A Cauer elliptic filter
of type CC051042 (see datasheet text) is used to guarantee these specific filter accuracy specifications. It is assumed that all other configurations
available in PAC-Designer will exhibit equivalent performance according to the applicability of the individual filter type. Necessary limitations will
apply, however, when specifications do not directly apply. See the data sheet text, application notes and guides in PAC-Designer for specific filter
type considerations.
3
Specifications
ispPAC80
Absolute Maximum Ratings
Supply Voltage V
S
....................................... -0.5 to +7V
Logic and Analog Input Voltage Applied ........... 0 to V
S
Logic and Analog Output Short Circuit Duration ..... Indefinite
Lead Temperature (Soldering, 10 sec.) .............. 260°C
Ambient Temperature with Power Applied ... -55 to 125°C
Storage Temperature ................................ -65 to 150°C
Note: Stresses above those listed may cause permanent
damage to the device. These are stress only ratings and
functional operation of the device at these or at any other
conditions above those indicated in the operational sec-
tions of this specification is not implied.
Package Options
1
16-pin PDIP
Part Number Description
ispPAC 80 – XX X X
Device Family
Device Number
Performance Grade
01 = Standard
Package
P = PDIP, S = SOIC
Grade
I = Industrial Temperature
ispPAC 80
1
16-pin SOIC
ispPAC 80
ispPAC80 Ordering Information
Ordering Number
ispPAC80-01PI
ispPAC80-01SI
Package
16-Pin PDIP
16-Pin SOIC
4
Specifications
ispPAC80
Timing Specifications (JTAG Interface Mode)
T
A
= 25
°
C; V
S
= +5.0V (Unless otherwise specified)
Symbol
Dynamic Performance
Parameter
Condition
Min.
Typ.
Max.
Units
tckmin
tckh
tckl
tmss
tmsh
tdis
tdih
tdozx
tdov
tdoxz
tpwp
tpwe
tpwcal1
tcalmin
tpwcal2
Minimum Clock Period
TCK High Time
TCK Low Time
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
TDO Float to Valid Delay
TDO Valid Delay
TDO Valid to Float Delay
Time for a programming operation
Executed in Run-Test/Idle
Time for an erase operation
Executed in Run-Test/Idle
Time for auto-cal operation on power-up Automatically executed at power-up
Minimum auto-cal pulse width
Time for user initiated auto-cal operation
Executed on rising edge of CAL
tckh
tckl
tckmin
TCK
200
50
50
15
10
15
10
60
60
60
100
100
250
100
80
80
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ns
ms
tpwp, tpwe
TCK
tmss
tmsh
tmss
*(PRGUSR/UBE executed in
Run-Test/Idle state)
tmss
TMS
tdis
tdih
TMS
TDI
tdozx
tdov
tdoxz
CAL
tcalmin
(Note: CAL internally
initiated at device turn-on.)
V
OUT
= 0V
DIFF
TDO
VOUT
tpwcal1, tpwcal2
*Note: During device JTAG programming, analog output response will deviate from expected behavior. This is because all
configuration information is erased and then re-written as part of a normal programming cycle, momentarily changing device filter
and gain parameters. Behavior will deviate from that expected during both of these steps since the analog outputs are not clamped
during a programming cycle. During erase, a drop in the filter corner frequency and an automatic change to the 10X gain setting
can be expected (80ms minimum by specification) and will continue until bits go to there final state after a JTAG write command
is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve specified data retention).
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