FSGYE035R
Data Sheet
December 2001
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFET
Fairchild Star*Power™ Rad Hard
MOSFETs have been specifically
TM
developed for high performance
applications in a commercial or
military space environment.
Star*Power MOSFETs offer the system designer both
extremely low r
DS(ON)
and Gate Charge allowing the
development of low loss Power Subsystems. Star*Power
Gold FETs combine this electrical capability with total dose
radiation hardness up to 100 krads while maintaining the
guaranteed performance for Single Event Effects (SEE)
which the Fairchild FS families have always featured.
The Fairchild family of Star*Power FETs includes a series of
devices in various voltage, current and package styles. The
portfolio consists of Star*Power and Star*Power Gold
products. Star*Power FETs are optimized for total dose and
r
DS(ON)
while exhibiting SEE capability at full rated voltage
up to an LET of 37. Star*Power Gold FETs have been
optimized for SEE and Gate Charge combining SEE
performance to 80% of the rated voltage for an LET of 82
with extremely low gate charge characteristics.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is specifically designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, power
distribution, motor drives and relay drivers as well as other
power control and conditioning applications. As with
conventional MOSFETs these Radiation Hardened
MOSFETs offer ease of voltage control, fast switching
speeds and ability to parallel switching devices.
Reliability screening is available as either TXV or Space
equivalent of MIL-PRF-19500.
Formerly available as type TA45224W.
Features
• 20A (Current Limited by Package), 60V, r
DS(ON)
= 0.030Ω
• UIS Rated
• Total Dose
- Meets Pre-Rad Specifications to 100 krad (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 82MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown
• Dose Rate
- Typically Survives 3E9 Rad (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
AS
• Photo Current
- 1.2nA Per-Rad (Si)/s Typically
• Neutron
- Maintain Pre-Rad Specifications
for 3E13 Neutrons/cm
2
- Usable to 3E14 Neutrons/cm
2
Symbol
D
G
S
Packaging
SMD.5
Ordering Information
RAD LEVEL
10K
100K
100K
SCREENING LEVEL
PART NUMBER/BRAND
Engineering Samples FSGYE035D1
TXV
Space
FSGYE035R3
FSGYE035R4
©2001 Fairchild Semiconductor Corporation
FSGYE035R Rev. B
FSGYE035R
Absolute Maximum Ratings
Drain to Source Voltage
Drain to Gate Voltage (R
GS
= 20kΩ)
Continuous Drain Current
T
C
= 25
o
C
T
C
= 100
o
C
Pulsed Drain Current
Gate to Source Voltage
Maximum Power Dissipation
T
C
= 25
o
C
T
C
= 100
o
C
Linear Derating Factor
Single Pulsed Avalanche Current, L = 100µH (See Test Figure)
Continuous Source Current (Body Diode)
Pulsed Source Current (Body Diode)
Operating and Storage Temperature
Lead Temperature (During Soldering)
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical)
I
AS
I
S
I
SM
T
J
, T
STG
T
L
P
T
P
T
42
17
0.33
57
20
80
-55 to 150
300
1.0 (Typical)
W
W
W/
o
C
A
A
A
o
C
o
C
T
C
= 25
o
C, Unless Otherwise Specified
FSGYE035R
V
DS
V
DGR
I
D
I
D
I
DM
V
GS
60
60
20 (Note)
20 (Note)
80
±30
UNITS
V
V
A
A
A
V
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: Current is limited by the package capability
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
60
-
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 12V
V
DD
= 30V,
I
D
= 20A
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 2V
I
D
= 20A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.025
-
-
-
-
-
24
10
5
56
3
6
1550
540
13
-
MAX
-
5.5
4.5
-
25
250
100
200
0.600
0.030
0.051
20
55
30
15
28
12
7
-
-
-
-
-
-
1.67
UNITS
V
V
V
V
µA
µA
nA
nA
V
Ω
Ω
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(12)
Q
gs
Q
gd
Q
g(20)
Q
g(TH)
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= 48V,
V
GS
= 0V
V
GS
=
±30V
V
GS
= 12V, I
D
= 20A
I
D
= 20A,
V
GS
= 12V
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge Source
Gate Charge Drain
Gate Charge at 20V
Threshold Gate Charge
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
V
DD
= 30V, I
D
= 20A,
R
L
= 1.5Ω, V
GS
= 12V,
R
GS
= 7.5Ω
©2001 Fairchild Semiconductor Corporation
FSGYE035R Rev. B
FSGYE035R
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
SYMBOL
V
SD
t
rr
Q
RR
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±30V,
V
DS
= 0V
V
GS
= 0, V
DS
= 48V
V
GS
= 12V, I
D
= 20A
V
GS
= 12V, I
D
= 20A
MIN
60
2.0
-
-
-
-
MAX
-
4.5
100
25
0.600
0.030
UNITS
V
V
nA
µA
V
Ω
I
SD
= 20A
I
SD
= 20A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
0.31
MAX
1.2
110
-
UNITS
V
ns
µC
Electrical Specifications up to 100 krad
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
(NOTE 6)
TYPICAL LET
(MeV/mg/cm)
37
60
60
82
82
NOTES:
4. Testing conducted at Brookhaven National Labs or Texas A&M.
5. Fluence = 1E5 ions/cm
2
(typical), T = 25
o
C.
6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au.
7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
APPLIED
V
GS
BIAS
(V)
-5
-2
-4
0
-2
(NOTE 7)
MAXIMUM
V
DS
BIAS
(V)
60
60
30
48
30
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
TYPICAL RANGE (µ)
36
32
32
28
28
Performance Curves
Unless Otherwise Specified
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LET = 60MeV/mg/cm
2
, RANGE = 32µ
LET = 82MeV/mg/cm
2
, RANGE = 28µ
70
60
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
70
60
50
LET = 37
50
V
DS
(V)
40
30
20
20
10
10
0
0
-1
-2
-3
V
GS
(V)
-4
-5
-6
0
0
5
LET = 60
10
15
20
25
30
35
40
LET = 82
V
DS
(V)
40
30
NEGATIVE V
GS
BIAS (V)
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. TYPICAL SEE SIGNATURE CURVE
©2001 Fairchild Semiconductor Corporation
FSGYE035R Rev. B
FSGYE035R
Performance Curves
1E-3
LIMITING INDUCTANCE (HENRY)
Unless Otherwise Specified
(Continued)
24
20
1E-4
I
D
, DRAIN (A)
ILM = 10A
30A
1E-5
100A
300A
1E-6
4
0
-50
16
12
8
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO
LIMIT GAMMA DOT CURRENT TO I
AS
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
200
100
I
D
, DRAIN CURRENT (A)
T
C
= 25
o
C
100µs
12V
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1ms
Q
GS
10ms
V
G
Q
GD
Q
G
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
200
CHARGE
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. BASIC GATE CHARGE WAVEFORM
2.5
I
D
, DRAIN TO SOURCE CURRENT (A)
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 20A
2.0
NORMALIZED r
DS(ON)
100
V
GS
= 14V
V
GS
= 12V
V
GS
= 10V
V
GS
= 8V
80
1.5
60
1.0
40
V
GS
= 6V
20
0.5
0
-80
-40
0
40
80
120
160
0
0
2
4
6
8
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 7. TYPICAL NORMALIZED r
DS(ON)
vs JUNCTION
TEMPERATURE
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
FSGYE035R Rev. B
FSGYE035R
Performance Curves
NORMALIZED THERMAL RESPONSE (Z
θJC
)
10
Unless Otherwise Specified
(Continued)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
+ T
C
10
-4
10
-3
10
-2
10
-1
10
0
P
DM
t
1
0.1
t
2
10
1
0.001
10
-5
t, RECTANGULAR PULSE DURATION (s)
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
200
I
AS
, AVALANCHE CURRENT (A)
100
STARTING T
J
= 25
o
C
10
STARTING T
J
= 150
o
C
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
≠
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
1
0.01
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
≤
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSGYE035R Rev. B
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