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PA28F400BX-B60

Description
4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY
Categorystorage    storage   
File Size571KB,50 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

PA28F400BX-B60 Overview

4-MBIT (256K X 16, 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY

PA28F400BX-B60 Parametric

Parameter NameAttribute value
Parts packaging codeSOIC
package instruction1.110 X 0.525 INCH, PLASTIC, SOP-40
Contacts40
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time60 ns
Other featuresBOTTOM BOOT BLOCK
Spare memory width8
startup blockBOTTOM
command user interfaceYES
Data pollingNO
JESD-30 codeR-PDSO-N40
length28.2 mm
memory density4194304 bi
Memory IC TypeFLASH
memory width16
Number of functions1
Number of departments/size1,2,1,3
Number of terminals40
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Encapsulate equivalent codeSOP44,.63
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Programming voltage12 V
Certification statusNot Qualified
Maximum seat height2.95 mm
Department size16K,8K,96K,128K
Maximum standby current0.0000012 A
Maximum slew rate0.065 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationDUAL
switch bitNO
typeNOR TYPE
width13.3 mm
Base Number Matches1
4-MBIT (256K X 16 512K X 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F400BX-T B 28F004BX-T B
Y
x8 x16 Input Output Architecture
28F400BX-T 28F400BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
x8-only Input Output Architecture
28F004BX-T 28F004BX-B
For Space Constrained 8-bit
Applications
Upgradeable to Intel’s Smart Voltage
Products
Optimized High-Density Blocked
Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
Extended Cycling Capability
100 000 Block Erase Cycles
Automated Word Byte Write and Block
Erase
Command User Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Y
Very High-Performance Read
60 80 120 ns Maximum Access Time
30 40 40 ns Maximum Output Enable
Time
Low Power Consumption
20 mA Typical Active Read Current
Reset Deep Power-Down Input
0 2
mA
I
CC
Typical
Acts as Reset for Boot Operations
Extended Temperature Operation
b
40 C to
a
85 C
Write Protection for Boot Block
Hardware Data Protection Feature
Erase Write Lockout During Power
Transitions
Industry Standard Surface Mount
Packaging
28F400BX JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
28F004BX 40-Lead TSOP
12V Word Byte Write and Block Erase
V
PP
e
12V
g
5% Standard
V
PP
e
12V
g
10% Option
ETOX
TM
III Flash Technology
5V Read
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290451-005

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