EEWORLDEEWORLDEEWORLD

Part Number

Search

PA28F400BV-T60

Description
2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Categorystorage    storage   
File Size414KB,55 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

PA28F400BV-T60 Overview

2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PA28F400BV-T60 Parametric

Parameter NameAttribute value
Parts packaging codeSOIC
package instructionSOP,
Contacts44
Reach Compliance Codeunknow
Maximum access time110 ns
Other featuresCAN BE OPERATED IN 4.5V TO 5.5V; CAN BE CONFG AS 256K X 16; TOP BOOT BLOCK
JESD-30 codeR-PDSO-G44
length28.2 mm
memory density4194304 bi
Memory IC TypeFLASH
memory width8
Number of functions1
Number of terminals44
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height2.95 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width13.3 mm
Base Number Matches1
E
n
n
n
n
n
n
SEE NEW DESIGN RECOMMENDATIONS
REFERENCE ONLY
2-MBIT SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
Intel SmartVoltage Technology
5 V or 12 V Program/Erase
3.3 V or 5 V Read Operation
Very High-Performance Read
5 V: 60 ns Access Time
3 V: 110 ns Access Time
Low Power Consumption
Max 60 mA Read Current at 5 V
Max 30 mA Read Current at
3.3 V–3.6 V
x8/x16-Selectable Input/Output Bus
28F200 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F002B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
Extended Temperature Operation
–40 °C to +85 °C
n
n
Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
Reset/Deep Power-Down Input
0.2 µA I
CC
Typical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-, 48-, 56-Lead TSOP
44-Lead PSOP
Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
n
n
n
n
n
n
n
n
New Design Recommendations:
For new 2.7 V–3.6 V V
CC
designs with this device, Intel recommends using the Smart 3 Advanced Boot
Block. Reference
Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family
datasheet,
order number 290580.
For new 5 V V
CC
designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference
Smart 5 Flash Memory Family 2, 4, 8 Mbit
datasheet, order number 290599.
These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.
December 1997
Order Number: 290531-005
Guidance: What should I learn if I want to develop in the hardware field in the electronic information major?
I am a student majoring in electronic information and I want to study for a master's degree. I personally prefer hardware-related things and hate programming. Although hardware also requires programmi...
zhaolequan Embedded System
Common protection circuit design
Protection circuit design...
tonytong Power technology
PCB production of nRF905
I am now drawing a nRF905 module circuit. Anyone who has personally made nRF905 PCB can give me some help? Now I have some questions: Does this support 433, 868 and 915 frequency bands? It seems that ...
melodyooo RF/Wirelessly
Dual-channel data acquisition based on ARM
The input end is connected to a function signal generator. How do I write square waves, sine waves, triangle waves, etc. based on LM3S9B96 and display them on the screen?...
L_古斯 ARM Technology
s7-200 programming cable problem
I have many Siemens PLCs that use S7-200, but I don't have a programming cable. Now some machines need programming. I have a RS232-RS485 converter for Siwei inverters. I don't know if it can be used o...
eeleader Industrial Control Electronics
Typical Questions about Clock Gating
In my design , the main internal working clock is provided after the reset is cancelled. My original design expected that when the reset is cancelled, all flip-flops would be asynchronously reset to a...
eeleader-mcu FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2123  1562  2704  560  1627  43  32  55  12  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号