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PA28F200BV-T60

Description
2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Categorystorage    storage   
File Size414KB,55 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

PA28F200BV-T60 Overview

2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

PA28F200BV-T60 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instruction0.525 X 1.110 INCH, PLASTIC, SOP-44
Contacts44
Reach Compliance Codeunknow
ECCN codeEAR99
Maximum access time110 ns
Other featuresCAN BE OPERATED IN 4.5V TO 5.5V; CAN BE CONFG AS 128K X 16; TOP BOOT BLOCK
Spare memory width8
startup blockTOP
command user interfaceYES
Data pollingNO
Durability100000 Write/Erase Cycles
JESD-30 codeR-PDSO-G44
JESD-609 codee0
length28.2 mm
memory density2097152 bi
Memory IC TypeFLASH
memory width8
Number of functions1
Number of departments/size1,2,1,1
Number of terminals44
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP44,.63
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply3.3/5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height2.95 mm
Department size16K,8K,96K,128K
Maximum standby current0.000008 A
Maximum slew rate0.065 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
switch bitNO
typeNOR TYPE
width13.3 mm
Base Number Matches1
E
n
n
n
n
n
n
SEE NEW DESIGN RECOMMENDATIONS
REFERENCE ONLY
2-MBIT SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
Intel SmartVoltage Technology
5 V or 12 V Program/Erase
3.3 V or 5 V Read Operation
Very High-Performance Read
5 V: 60 ns Access Time
3 V: 110 ns Access Time
Low Power Consumption
Max 60 mA Read Current at 5 V
Max 30 mA Read Current at
3.3 V–3.6 V
x8/x16-Selectable Input/Output Bus
28F200 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F002B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
Extended Temperature Operation
–40 °C to +85 °C
n
n
Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
Reset/Deep Power-Down Input
0.2 µA I
CC
Typical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-, 48-, 56-Lead TSOP
44-Lead PSOP
Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
n
n
n
n
n
n
n
n
New Design Recommendations:
For new 2.7 V–3.6 V V
CC
designs with this device, Intel recommends using the Smart 3 Advanced Boot
Block. Reference
Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family
datasheet,
order number 290580.
For new 5 V V
CC
designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference
Smart 5 Flash Memory Family 2, 4, 8 Mbit
datasheet, order number 290599.
These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.
December 1997
Order Number: 290531-005
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