533BB000339DGR datasheet, PDF - EEWORLD Datasheet

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533BB000339DGR: DescriptionLVDS Output Clock Oscillator, 10MHz Min, 945MHz Max,; CategoryPassive components oscillator; File Size439KB，12 Pages; ManufacturerSkyworks; Websitehttp://www.skyworksinc.com; Environmental Compliance

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533BB000339DGR Overview

LVDS Output Clock Oscillator, 10MHz Min, 945MHz Max,

533BB000339DGR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	4037669870
Reach Compliance Code	compliant
Other features	TRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; SELECTABLE O/P FREQ
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	6
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
Output load	100 OHM
Encapsulate equivalent code	DILCC6,.2
physical size	7.0mm x 5.0mm x 1.8mm
longest rise time	0.35 ns
Filter level	MIL-STD-883
Maximum slew rate	98 mA
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Gold (Au) - with Nickel (Ni) barrier

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Si533

EVISION

U A L

REQUENCY

R Y S TA L

SCILLATOR

(X O )

(10 M H

Z TO

1 . 4 G H

)

Features



Available with any-frequency output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

2 selectable output frequencies



3rd generation DSPLL with superior



jitter performance



3x better frequency stability than

SAW-based oscillators



Pin 1 output enable (OE)

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications

SONET/SDH



Networking



SD/HD video



Ordering Information:

Clock and data recovery



FPGA/ASIC clock generation



See page 7.

Description

The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si533

is available with any-frequency output frequency from 10 to 945 MHz and

select frequencies to 1400 MHz. Unlike a traditional XO, where a different

crystal is required for each output frequency, the Si533 uses one fixed crystal

to provide a wide range of output frequencies. This IC based approach allows

the crystal resonator to provide exceptional frequency stability and reliability.

In addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low jitter clocks in noisy environments

typically found in communication systems. The Si533 IC based XO is factory

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, and temperature stability. Specific

configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

Pin Assignments:

See page 6.

(Top View)

GND

CLK–

CLK+

LVDS/LVPECL/CML

Functional Block Diagram

CLK– CLK+

CMOS

CLK+

Fixed

Frequency

Any-frequency

10–1400 MHz

DSPLL®

Clock

Synthesis

GND

Rev. 1.4 6/18

Si533

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