Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
DESCRIPTION
The 89C51/89C52/89C54/89C58 contain a non-volatile FLASH
program memory that is parallel programmable. For devices that are
serial programmable (In System Programmable (ISP) with a boot
loader), see the 89C51RC+/89C51RD+ datasheet.
Both families are Single-Chip 8-bit Microcontrollers manufactured in
advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set
as the 80C51.
FEATURES
SELECTION TABLE FOR FLASH DEVICES
ROM/EPROM
Memory Size
(X by 8)
RAM Size
(X by 8)
Programmable
Timer Counter
(PCA)
Hardware
Watchdog
Timer
•
80C51 Central Processing Unit
•
On-chip FLASH Program Memory
•
Speed up to 33 MHz
•
Full static operation
•
RAM expandable externally to 64 k bytes
•
4 level priority interrupt
•
6 interrupt sources
•
Four 8-bit I/O ports
•
Full-duplex enhanced UART
–
Framing error detection
–
Automatic address recognition
Multi-Time Programmable (MTP) devices:
89C51
4k
89C52/54/58
8 k/16 k/32 k
89C51RC+
32 k
89C51RD+
64 k
1024
Yes
Yes
512
Yes
Yes
256
No
No
Serial In-System Programmable devices:
128
No
No
•
Power control modes
–
Clock can be stopped and resumed
–
Idle mode
–
Power down mode
•
Programmable clock out
•
Second DPTR register
•
Asynchronous port reset
•
Low EMI (inhibit ALE)
•
3 16-bit timers
•
Wake up from power down by an external interrupt
ORDERING INFORMATION
MEMORY SIZE
4k
×
8
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
P89C51UBA A
P89C51UBP N
P89C51UBB B
P89C51UFA A
P89C51UFP N
P89C51UFB B
MEMORY SIZE
8k
×
8
P89C52UBA A
P89C52UBP N
P89C52UBB B
P89C52UFA A
P89C52UFP N
P89C52UFB B
MEMORY SIZE
16 k
×
8
P89C54UBA A
P89C54UBP N
P89C54UBB B
P89C54UFA A
P89C54UFP N
P89C54UFB B
MEMORY SIZE
32 k
×
8
P89C58UBA A
P89C58UBP N
P89C58UBB B
P89C58UFA A
1
P89C58UFP N
1
P89C58UFB B
1
TEMPERATURE
RANGE
°C
AND PACKAGE
0 to +70, Plastic
Leaded Chip Carrier
0 to +70, Plastic
Dual In-line Package
0 to +70, Plastic
Quad Flat Pack
–40 to +85, Plastic
Leaded Chip Carrier
–40 to +85, Plastic
Dual In-line Package
–40 to +85, Plastic
Quad Flat Pack
VOLTAGE
RANGE
5V
5V
5V
5V
5V
5V
FREQ.
(MHz)
0 to 33
0 to 33
0 to 33
0 to 33
0 to 33
0 to 33
DWG.
#
SOT187-2
SOT129-1
QFP44
2
SOT187-2
SOT129-1
QFP44
2
NOTES:
1. Contact Philips Sales for availability.
2. SOT not assigned for this package outline.
PART NUMBER DERIVATION
DEVICE NUMBER (P89CXX)
P89C51 FLASH
P89C52 FLASH
P89C54 FLASH
P89C58 FLASH
U = 33 MHz
B = 0_C to 70_C
F = –40_C to 85_C
OPERATING FREQUENCY, MAX (V)
TEMPERATURE RANGE (B)
PACKAGE (AA, BB, PN)
AA = PLCC
BB = PQFP
PN = PDIP
1999 Oct 27
2
853–2148 22592
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
89C51/89C52/89C54/89C58
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
CC
P0.0–0.7
DIP
20
40
39–32
LCC
22
44
43–36
QFP
16
38
37–30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0 V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I
IL
). Alternate function for Port 1:
T2 (P1.0):
Timer/Counter2 external count input/clockout (see Programmable Clock-Out).
T2EX (P1.1):
Timer/Counter2 reload/capture/direction control.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of the
89C51/89C52/89C54/89C58, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
CC
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable:
The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage:
EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to the
maximum internal memory boundary. If EA is held high, the device executes from internal
program memory unless the program counter contains an address greater than 0FFFH for
4 k devices, 1FFFH for 8 k devices, 3FFFH for 16 k devices, and 7FFFH for 32 k devices.
The value on the EA pin is latched when RST is released and any subsequent changes
have no effect. This pin also receives the 12.00 V programming supply voltage (V
PP
) during
FLASH programming.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
1
2
P2.0–P2.7
21–28
2
3
24–31
40
41
18–25
I/O
I
I/O
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
RST
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
33
27
O
PSEN
29
32
26
O
EA/V
PP
31
35
29
I
XTAL1
XTAL2
19
18
21
20
15
14
I
O
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin (other than V
PP
) at any time must not be higher than V
CC
+ 0.5 V or
V
SS
– 0.5 V, respectively.
1999 Oct 27
5
Embedded System
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