INTEGRATED CIRCUITS
P89C51RC+/P89C51RD+
80C51 8-bit Flash microcontroller family
32K/64K ISP FLASH with 512–1K RAM
Product specification
Replaces 89C51RC+/RD+ of 1999 Apr 01
(see Notes 1 and 2 on page 2)
Supersedes data of 1999 Apr 01
1999 Oct 27
IC28 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
80C51 8-bit Flash microcontroller family
32K/64K ISP FLASH with 512–1K RAM
P89C51RC+/P89C51RD+
DESCRIPTION
The 89C51RX+ devices contain a non-volatile FLASH program
memory (up to 64 k bytes in the 89C51RD+) that is both parallel
programmable and Serial In-System Programmable. In-System
Programming allows devices to alter their own program memory, in
the actual end product, under software control. This opens up a
range of applications that can include the ability to field update the
application firmware.
A default serial loader (boot loader) program in ROM allows
In-System serial programming of the FLASH memory without the
need for a loader in the FLASH code. User programs may erase and
reprogram the FLASH memory at will through the use of standard
routines contained in ROM.
These devices are Single-Chip 8-Bit Microcontrollers manufactured
in advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set
as the 80C51.
FLASH/EPROM
Memory Size
(X by 8)
89C51RC+
32 k
89C51RD+
64 k
1024
Yes
512
Yes
RAM Size
(X by 8)
Programmable
Timer Counter
(PCA)
FEATURES
•
80C51 Central Processing Unit
•
On-chip FLASH Program Memory with In-System Programming
(ISP) capability
•
Boot ROM contains low level FLASH programming routines and a
default serial loader
•
Speed up to 33 MHz
•
Full static operation
•
RAM expandable externally to 64 k bytes
•
4 level priority interrupt
•
7 interrupt sources, depending on device
•
Four 8-bit I/O ports
•
Full-duplex enhanced UART
–
Framing error detection
–
Automatic address recognition
•
Power control modes
–
Clock can be stopped and resumed
–
Idle mode
–
Power down mode
See P89C51RX2 data sheet for devices which do not require a 12 V
programming voltage.
The devices also have four 8-bit I/O ports, three 16-bit timer/event
counters, a multi-source, four-priority-level, nested interrupt
structure, an enhanced UART and on-chip oscillator and timing
circuits. For systems that require extra memory capability up to
64 k bytes, each can be expanded using standard TTL-compatible
memories and logic.
The added features of the P89C51RX+ Family makes them even
more powerful microcontrollers for applications that require pulse
width modulation, high-speed I/O and up/down counting capabilities
such as motor control.
•
Programmable clock out
•
Second DPTR register
•
Asynchronous port reset
•
Low EMI (inhibit ALE)
•
Watchdog timer
ORDERING INFORMATION
MEMORY SIZE
32 k
×
8
P89C51RC+IN
P89C51RC+IA
P89C51RC+IB
P89C51RC+JN
P89C51RC+JA
P89C51RC+JB
MEMORY SIZE
64 k
×
8
P89C51RD+IN
P89C51RD+IA
P89C51RD+IB
P89C51RD+JN
P89C51RD+JA
P89C51RD+JB
TEMPERATURE RANGE
°C
AND PACKAGE
0 to +70,
40-Pin Plastic Dual In-line Pkg.
0 to +70,
44-Pin Plastic Leaded Chip Carrier
0 to +70,
44-Pin Plastic Quad Flat Pack
–40 to +85,
40-Pin Plastic Dual In-line Pkg.
–40 to +85,
44-Pin Plastic Leaded Chip Carrier
–40 to +85,
44-Pin Plastic Quad Flat Pack
VOLTAGE
RANGE
5V
5V
5V
5V
5V
5V
FREQ.
(MHz)
0 to 33
0 to 33
0 to 33
0 to 33
0 to 33
0 to 33
DWG.
#
SOT129-1
SOT187-2
QFP44
1
SOT129-1
SOT187-2
QFP44
1
NOTE:
1. SOT not assigned for this package outline.
1999 Oct 27
2
853-2149 22593
Philips Semiconductors
Product specification
80C51 8-bit Flash microcontroller family
32K/64K ISP FLASH with 512–1K RAM
P89C51RC+/P89C51RD+
ORDERING INFORMATION
DEVICE NUMBER (P89C51RC+)
P89C51RC+ (FLASH)
P89C51RD+ (FLASH)
TEMPERATURE RANGE/OPERATING
FREQUENCY, MAX (I)
I = 33 MHz, 0_C to 70_C
J = 33 MHz, –40_C to +85_C
PACKAGE (A)
A = PLCC
B = PQFP
N = PDIP
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
V
CC
V
SS
RAM ADDR
REGISTER
RAM
PORT 0
LATCH
PORT 2
DRIVERS
PORT 2
LATCH
FLASH
8
B
REGISTER
STACK
POINTER
ACC
TMP2
TMP1
PROGRAM
ADDRESS
REGISTER
ALU
SFRs
TIMERS
PSW
P.C.A.
8
BUFFER
PC
INCRE-
MENTER
16
PROGRAM
COUNTER
PSEN
ALE
EAV
PP
RST
PD
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR’S
MULTIPLE
PORT 1
LATCH
PORT 3
LATCH
OSCILLATOR
PORT 1
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
PORT 3
DRIVERS
P3.0–P3.7
SU01065
1999 Oct 27
3
Philips Semiconductors
Product specification
80C51 8-bit Flash microcontroller family
32K/64K ISP FLASH with 512–1K RAM
P89C51RC+/P89C51RD+
LOGIC SYMBOL
V
CC
XTAL1
V
SS
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6
1
40
7
PORT 0
ADDRESS AND
DATA BUS
LCC
39
XTAL2
T2
T2EX
RST
EA/V
PP
PSEN
SECONDARY FUNCTIONS
ALE/PROG
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 1
17
29
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
NIC*
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
28
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
PORT 3
PORT 2
ADDRESS BUS
SU00830
PIN CONFIGURATIONS
DUAL IN-LINE PACKAGE PIN FUNCTIONS
* NO INTERNAL CONNECTION
SU00890
T2/P1.0 1
T2EX/P1.1 2
ECI/P1.2 3
CEX0/P1.3 4
CEX1/P1.4 5
CEX2/P1.5 6
CEX3/P1.6 7
CEX4/P1.7 8
RST 9
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
V
SS
20
DUAL
IN-LINE
PACKAGE
40 V
CC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
1
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
11
33 P0.6/AD6
32 P0.7/AD7
31 EA/V
PP
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
12
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Function
V
SS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NIC*
EA/V
PP
P0.7/AD7
22
PQFP
33
23
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
CC
NIC*
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3/CEX0
P1.4/CEX1
* NO INTERNAL CONNECTION
SU00891
SU00888
1999 Oct 27
4
Philips Semiconductors
Product specification
80C51 8-bit Flash microcontroller family
32K/64K ISP FLASH with 512–1K RAM
P89C51RC+/P89C51RD+
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
CC
P0.0–0.7
DIP
20
40
39–32
LCC
22
44
43–36
QFP
16
38
37–30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0 V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I
IL
).
Alternate functions for 89C51RX+ Port 1 include:
1
2
3
4
5
6
7
8
P2.0–P2.7
21–28
2
3
4
5
6
7
8
9
24–31
40
41
42
43
44
1
2
3
18–25
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
T2 (P1.0):
Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out)
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction Control
ECI (P1.2):
External Clock Input to the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of the
89C51RX+ family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal resistor to V
SS
permits a power-on reset using only an external capacitor
to V
CC
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
RST
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
33
27
O
1999 Oct 27
5
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