Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
DESCRIPTION
The Philips 80C575/83C575/87C575 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The Philips CMOS technology combines the
high speed and density characteristics of
HMOS with the low power attributes of
CMOS. Philips epitaxial substrate minimizes
latch-up sensitivity.
The 8XC575 contains an 8k
×
8 ROM
(83C575) EPROM (87C575), a 256
×
8 RAM,
32 I/O lines, three 16-bit counter/timers, a
Programmable Counter Array (PCA), a
seven-source, two-priority level nested
interrupt structure, an enhanced UART, four
analog comparators, power-fail detect and
oscillator fail detect circuits, and on-chip
oscillator and clock circuits.
In addition, the 8XC575 has a low active
reset, and the port pins are reset to a low
level. There is also a fully configurable
watchdog timer, and internal power on clear
circuit. The part includes idle mode and
power-down mode states for reduced power
consumption.
FEATURES
•
80C51 based architecture
–
8k
×
8 ROM (83C575)
–
8k
×
8 EPROM (87C575)
–
ROMless (80C575)
–
256
×
8 RAM
–
Three 16-bit counter/timers
–
Programmable Counter Array
–
Enhanced UART
–
Boolean processor
–
Oscillator fail detect
–
Low active reset
–
Asynchronous low port reset
–
Schmitt trigger inputs
–
4 analog comparators
–
Watchdog timer
–
Low V
CC
detect
PIN CONFIGURATIONS
CMP0+/P1.0/T2
CMP0-/P1.1/T2EX
ECI/P1.2
CMP0/CEX0/P1.3
CMP1/CEX1/P1.4
CMP2/CEX2/P1.5
CMP3/CEX3/P1.6
CEX4/P1.7
RST
1
2
3
4
5
6
7
8
9
DUAL
IN-LINE
PACKAGE
40 V
DD
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA/V
PP
30 ALE/PROG
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
RxD/P3.0 10
TxD/P3.1
INT0/P3.2
INT1/P3.3
11
12
13
•
Memory addressing capability
–
64k ROM and 64k RAM
CMPR-/T0/P3.4 14
CMP1+/T1/P3.5 15
CMP2+/WR/P3.6 16
CMP3+/RD/P3.7 17
XTAL2
XTAL1
V
SS
18
19
20
•
Power control modes:
–
Idle mode
–
Power-down mode
•
CMOS and TTL compatible
•
4.0 to 16MHz
•
Extended temperature ranges
•
OTP package available
7
17
6
1
40
39
1
44
34
33
PQFP
LCC
29
18
28
11
12
23
22
SU00234
ORDERING INFORMATION
ROMless
P80C575EBP N
P80C575EBA A
P80C575EHAA
P80C575EBB B
ROM
P83C575EBP N
P83C575EBA A
P83C575EHAA
P83C575EBB B
EPROM
1
P87C575EBPN
P87C575EBAA
P87C575EHAA
P87C575EBBB
OTP
OTP
OTP
OTP
TEMPERATURE RANGE
°C
AND PACKAGE
0 to +70, 40-Pin Plastic Dual In-line Package
0 to +70, 44-Pin Plastic Leaded Chip Carrier
–40 to +125, 44-Pin Plastic Leaded Chip Carrier
0 to +70, 44-Pin Plastic Quad Flat Pack
FREQ
(MHz)
16
16
16
16
DRAWING
NUMBER
SOT129-1
SOT187-2
SOT187-2
SOT307-2
NOTE:
1. OTP - One Time Programmable EPROM.
1998 May 01
2
853-1684 19332
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
80C575/83C575/
87C575
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
CC
P0.0-0.7
DIP
20
40
39-32
LCC
22
44
43-36
QFP
16
38
37-30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
Port 0:
Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and data memory. In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code
bytes during EPROM programming and outputs code bytes during program verification.
External pull-ups are required during program verification. During reset, port 0 will be
asynchronously driven low and will remain low until written to by software. All port 0 pins
have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees
positive leakage current (see DC Electrical Characteristics: I
L1
).
Port 1:
Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that
pins that have 1s written to them can be used as inputs but will source current when
externally pulled low (see DC Electrical Characteristics: I
IL
). Port 1 receives the low-order
address byte during program memory verification and EPROM programming. During reset,
port 1 will be asynchronously driven low and will remain low until written to by software. All
port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve
alternate functions as follows:
P1.0 T2
Timer 2 external I/O – clockout (programmable)
CMP0+
Comparator 0 positive input
P1.1 T2EX
Timer 2 capture input
CMP0-
Comparator 0 negative input
P1.2 ECI
PCA count input
P1.3 CEX0
PCA module 0 external I/O
CMP0
Comparator 0 output
P1.4 CEX1
PCA module 1 external I/O
CMP1
Comparator 1 output
P1.5 CEX2
PCA module 2 external I/O
CMP2
Comparator 2 output
P1.6 CEX3
PCA module 3 external I/O
CMP3
Comparator 3 output
P1.7 CEX4
PCA module 4 external I/O
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them can be used as inputs, but will source current when externally pulled low
(see DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte during
accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2
receives the high-order address byte during program verification and EPROM programming.
During reset, port 2 will be asynchronously driven low and will remain low until written to by
software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open
drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC
Electrical Characteristics I
L1
).
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1
that have 1s written to them can be used as inputs but will source current when externally
pulled low (see DC Electrical Characteristics: I
IL
). P3.1 will be a high impedance pin except
while transmitting serial data, in which case the strong pull-up will remain on continuously
when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of
two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be
asynchronously driven low and will remain low until written to by software. All port 3 pins
have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV
hysteresis. Port 3 pins serve alternate functions as follows:
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
1
2
3
4
5
6
7
8
P2.0-P2.7
21-28
2
3
4
5
6
7
8
9
24-31
40
41
42
43
44
1
2
3
18-25
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
1998 May 01
5
Embedded System
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EEWORLD
