Philips Semiconductors
Preliminary specification
Single-chip 8-bit microcontroller
P83CE559/P80CE559
1. FEATURES
•
80C51 central processing unit
•
48 K
×
8 ROM, expandable externally to 64 Kbytes
•
ROM Code protection
•
1536
×
8 RAM, expandable externally to 64 Kbytes
•
Two standard 16-bit timer/counters
•
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
•
A 10-bit ADC with eight multiplexed analog inputs and
programmable autoscan
2. GENERAL DESCRIPTION
The P80CE559/P83CE559 (hereafter generically referred to as
P8xCE559) single-chip 8-bit microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The P8xCE559 has the same instruction set
as the 80C51. Three versions of the derivative exist:
•
Two 8-bit resolution, pulse width modulation outputs
•
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
•
I
2
C-bus serial I/O port with byte oriented master and slave
functions
•
Full-duplex UART compatible with the standard 80C51
•
On-chip watchdog timer
•
15 interrupt sources with 2 priority levels (2 to 6 external sources
possible)
•
P83CE559 — 48 Kbytes mask programmable ROM
•
P80CE559 — ROMless version of the P83CE559
•
P89CE559 — not planned any longer
•
Extended temperature range (–40 to +85
°C)
•
4.5 to 5.5 V supply voltage range
•
Frequency range for 80C51–family standard oscillator: 3.5 MHz to
16 MHz
•
PLL oscillator with 32 kHz reference and software–selectable
system clock frequency
The P8xCE559 contains a non-volatile 48 Kbytes mask
programmable ROM (P83CE559), a volatile 1536
×
8 read/write
data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I
2
C-bus), a “watchdog” timer, an on-chip
oscillator and timing circuits. For systems that require extra
capability the P8xCE559 can be expanded using standard TTL
compatible memories and logic.
In addition, the P8xCE559 has two software selectable modes of
power reduction — Idle Mode and power-down mode. The Idle
Mode freezes the CPU while allowing the RAM, timers, serial ports,
and interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic as well as bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three- byte. With a 16 MHz system
clock, 58% of the instructions are executed in 0.75
µs
and 40% in
1.5
µs.
Multiply and divide instructions require 3
µs.
•
Seconds Timer
•
Software enable/disable of ALE output pulse
•
Electromagnetic compatibility improvements
•
Wake–up from Power–down by external or seconds interrupt
1996 Aug 06
2
Philips Semiconductors
Preliminary specification
Single-chip 8-bit microcontroller
P83CE559/P80CE559
3. ORDERING INFORMATION
PACKAGE
EXTENDED TYPE NUMBER
NAME
ROMless
P80CE559EBB
P80CE559EFB
ROM coded
P83CE559EBB/YYY
1
P83CE559EFB/YYY
1
QFP80
QFP80
Plastic Quad Flat Pack; 80 leads
Plastic Quad Flat Pack; 80 leads
SOT318-1
SOT318-1
3.5 to 16
3.5 to 16
0 to +70
–40 to +85
QFP80
QFP80
Plastic Quad Flat Pack; 80 leads
Plastic Quad Flat Pack; 80 leads
SOT318-1
SOT318-1
3.5 to 16
3.5 to 16
0 to +70
–40 to +85
DESCRIPTION
CODE
FREQUENCY
RANGE (MHz)
TEMPERATURE
RANGE (°C)
NOTE:
1. YYY denotes the ROM code number.
T0
3
T1
3
INT0
3
INT1
3
V
DD
V
SS
PWM0 PWM1 AV
SS
AV
REF
ADC0-7 SDA
5
SCL
+ –
AV
DD
ADEXS
SELXTAL1
6
7
DATA
MEMORY
256 x 8 RAM
+
1280 x 8 RAM
DUAL
PWM
I
2
C
SERIAL
I/O
RSTIN
XTAL1
XTAL2
EA
ALE
PSEN
3 WR
3
RD
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
PROGRAM
MEMORY
48 K x 8 ROM
1Kx8
boot ROM
ADC
80C51 CORE
EXCLUDING
ROM/RAM
8-BIT INTERNAL BUS
0
AD0-7
2
A8-15
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORTS
FOUR
16-BIT
CAPTURE
LATCHES
16
T2
16-BIT
TIMER/
EVENT
COUNT-
ERS
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
16
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCH–
DOG
TIMER
PLL
oscillator
+
”seconds”
timer
3
P0
P1
P2
P3
TxD
3
RxD
P5
P4
1
CT0I-CT3I
1
T2
RT2
1
4
EW XTAL3 XTAL4
CMSR0-CMSR5
RSTOUT
CMT0, CMT1
0
1
2
ALTERNATE FUNCTION OF PORT0
ALTERNATE FUNCTION OF PORT1
ALTERNATE FUNCTION OF PORT2
3
4
5
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
6
7
NOT PRESENT IN P80CE559
ONLY PRESENT IN P89CE559
Figure 1. Block diagram P8xCE559.
1996 Aug 06
3
Embedded System
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