TSC21020E-25MA datasheet, PDF - EEWORLD Datasheet

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TSC21020E-25MA: DescriptionMixed Signal Processor, 32-Bit Size, CMOS, CPGA223,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size481KB，37 Pages; ManufacturerAtmel (Microchip)

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TSC21020E-25MA Overview

Mixed Signal Processor, 32-Bit Size, CMOS, CPGA223,

TSC21020E-25MA Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
package instruction	PGA, PGA223,18X18
Reach Compliance Code	compliant
bit size	32
Format	FLOATING POINT
JESD-30 code	S-XPGA-P223
JESD-609 code	e0
Number of terminals	223
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	PGA
Encapsulate equivalent code	PGA223,18X18
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum slew rate	460 mA
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, MIXED
Base Number Matches	1

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TSC21020E

Radiation Tolerant 32/40–Bit IEEE Floating–Point

DSP Microprocessor

Introduction

TEMIC Semiconductors is manufacturing a radiation

tolerant version of the Analog Devices ADSP–21020

32/40–Bit Floating–Point DSP.

The product is pin and code compatible with ADI

product, making system development straight forward

and cost effective, using existing development tools and

algorithms.

Features

Superscalar IEEE Floating-Point-Processor

Off-Chip Harvard Architecture Maximizes Signal Processing

Performance

40 ns, 25 MIPS Instruction Rate, Single-Cycle Execution

75 MFLOPS Peak, 50 MFLOPS Sustained Performance

1024-Point Complex FFT Benchmark : 0.78 ms

Divide (y/x) : 240 ns

Inverse Square Root (1/√x) : 360 ns

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Formats, Integer and Fractional, with

80-Bit Accumulators

IEEE Exception Handling with Interrupt on Exception

Three Independent Computation Units : Multiplier, ALU,

and Barrel Shifter

Dual Data Address Generators with Indirect, Immediate,

Modulo, and Bit Reverse Addressing Modes

Two Off-Chip Memory Transfers in Parallel with Instruction

Fetch and Single-Cycle Multiply & ALU Operations

Multiply with Add & Subtract for FFT Butterfly

Computation

Efficient Program Sequencing with Zero-Overhead

Looping : Single-Cycle Loop Setup

Single-Cycle Register File Context Switch

15 (or 25) ns External RAM Access Time for

Zero-Wait-State, 40 ns Instruction Execution

IEEE JTAG Standard 1149.1 Test Access Port and On-Chip

Emulation Circuitry

223 CPGA package for breadboarding

256 Multi layer quad flat pack, flat leads, for flight models

Full compatible with Analog Devices ADSP-21020

Latch up better than 55 MeV

Total dose better than 50 Krad (Si)

SEU immunity better than 30 MeV/mg/cm

– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO

– Product licensed from Analog Devices Inc.

MHS

Rev. D (05 Mai 98)

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