SPARTAN-3 GENERATION FPGAs
Xilinx Spartan -3A FPGA Platform
The World’s Lowest-Cost I/O Optimized FPGAs
™
The Programmable Logic
Challenge of I/O Intensive
Designs
•
Traditional FPGAs are proportionate
between logic and I/O not being cost-
effective for I/O intensive designs
•
System designers need to quickly adapt
to fast-evolving I/O standards
•
High volume consumer applications
require low-cost and robust security
solutions
Xilinx is driving the multiple domain-optimized platforms for highly efficient and
optimal design solutions, instead of forcing inefficient, one-size-fits-all solutions on
significantly varying application requirements.
Spartan-3A Platform Key Features
Standard Low-Cost Features
The Spartan-3A FPGA platform is a full feature platform of five devices with
system gates ranging from 50K to 1.4M gates, and I/Os ranging from 108 to 502
I/Os, with density migration. The Spartan-3A FPGAs also support up to 576 Kbits of
fast-block RAM with byte-write enable, and up to 176 Kbits of distributed RAM.
The Xilinx FPGA Solution
•
The Spartan
™
-3A FPGAs were designed
for applications where I/O count and
capabilities matter more than logic density
•
The Spartan-3A platform delivers up to
502 I/Os with support for industry-leading
26 popular and emerging I/O standards
•
The industry’s first 90nm FPGA electronic
ID - Device DNA serial number provides
a cost-effective, robust mechanism to help
protect against reverse-engineering,
cloning and overbuilding
Additionally, there are built-in multipliers for efficient DSP implementation and
Digital Clock Managers (DCMs) for system level clock management functions.
Advance Features
The advance features in the Spartan-3A platform include unique Device DNA
serial number, support for 26 I/O standards, enhanced Multi-Boot capability
with watchdog timer, dual power management modes, and Dynamic Input
Delay for precise data-to-clock centering. These advance features significantly
help shorten design cycles and lower system cost.
Industry’s first 90nm FPGA Electronic Serial Numbering
Each FPGA includes a permanent unique Device DNA serial number that can be used to
safeguard both hardware and software IP. It is ideal for tracking production serial numbers,
product registrations and system ID. Customers have complete flexibility in implementing
custom algorithms for the security solutions that can significantly deter reverse-engineering,
cloning and overbuilding.
Corporate Headquarters
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Tel: 408-559-7778
Fax: 408-559-7114
Web: www.xilinx.com
Widest Support for I/O Standards
The Spartan-3A FPGA is especially suitable for display devices supporting both TMDS and
PPDS standards. With support for 26 popular single-ended and differential signaling stan-
dards including TMDS, PPDS, SSTL3 Class I & II, full hot-swap compliance, and pre-engi-
neered interface IP solutions such as PCI, PCI Express, USB, Firewire, CAN, SPI, I2C, etc, the
Spartan-3A platform provides an industry-leading connectivity solution.
Europe Headquarters
Xilinx Ireland
One Logic Drive
Citywest Business Campus
Saggart, County Dublin
Ireland
Tel: +353-1-464-0311
Fax: +353-1-464-0324
Web: www.xilinx.com
Japan
Art Village Osaki Central Tower 4F
1-2-2 Osaki, Shinagawa-ku
Tokyo Japan
Zip: 141-0032
Phone +81-36744-7777
Web: japan.xilinx.com
Comprehensive Configuration Capabilities
The Spartan-3A platform features enhanced Multi-Boot capability with watchdog timer for
guaranteed “golden” configuration. This enables intelligent recovery from configuration
errors and improves field upgradeability.
Flexible Power-Management Modes
A new Suspend mode provides a very flexible and effective way to preserve power. In this
mode, the power is comparable to quiescent current, and the configuration data as well as
flip-flop and RAM values are maintained. It also includes a fast wake-up mechanism and sys-
tem level synchronization across time domains.
Dynamic Input Delay
Selecting delay-length for both registered and combinatorial inputs allows for precise timing
relationship adjustment between clock and data. Combinatorial input delay can now also be
dynamically changed through the interconnect. Source synchronous designs will significantly
benefit from this feature.
Asia Pacific Pte. Ltd.
Xilinx, Asia Pacific
No. 3 Changi Business Park Vista, #04-01
Singapore 486051
Tel: (65) 6544-8999
Fax: (65) 6789-8886
Spartan-3A FPGA Platform
Device
System Gates
Logic Cells
Dedicated Multipliers
Block RAM Blocks
Block RAM Bits
Distributed RAM Bits
DCMs
I/O Standards
Max Differential I/O
Max Single Ended I/O
Device
TQ144 20 x 20 mm
FT256 17 x 17 mm
FG320 19 x 19 mm
FG400 21 x 21 mm
FG484 23 x 23 mm
FG676 27 x 27 mm
XC3S50A
50K
1,584
3
3
54K
11K
2
26
64
144
XC3S50A
108
144
195
248
195
251
311
311
372
375
502
XC3S200A
200K
4,032
16
16
288K
28K
4
26
112
248
XC3S200A
XC3S400A
400K
8,064
20
20
360K
56K
4
26
142
311
XC3S400A
XC3S700A
700K
13,248
20
20
360K
92K
8
26
165
372
XC3S700A
XC3S1400A
1400K
25,344
32
32
576K
176K
8
26
227
502
XC3S1400A
Web: www.xilinx.com
Package and I/O Offerings
Take the Next Step
Visit our website
www.xilinx.com/spartan3a
or call your local sale office or distributor for
more information about Spartan-3A FPGAs. To start your design immediately, download
your free ISE WebPACK
TM
design tools at
www.xilinx.com/ise.
To begin evaluating Spartan-3A
FPGAs, order your hardware development board at
www.xilinx.com/s3astarter
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brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of
their respective owners
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