EEWORLDEEWORLDEEWORLD

Part Number

Search

5T940-10NLGI8

Description
PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28
Categorylogic    logic   
File Size116KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric Compare View All

5T940-10NLGI8 Online Shopping

Suppliers Part Number Price MOQ In stock  
5T940-10NLGI8 - - View Buy Now

5T940-10NLGI8 Overview

PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28

5T940-10NLGI8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeQFN
package instructionGREEN, PLASTIC, VFQFPN-28
Contacts28
Manufacturer packaging codeVFQFPN
Reach Compliance Codeunknown
ECCN codeEAR99
series5T
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQCC-N28
JESD-609 codee3
length6 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals28
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVQCCN
Encapsulate equivalent codeLCC28,.24SQ,25
Package shapeSQUARE
Package formCHIP CARRIER, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.02 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formNO LEAD
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width6 mm
minfmax666.52 MHz
Base Number Matches1
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on Q
OUT
• Regenerated input clock or Q
OUT
/4 on Q
REG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode 0: Q
OUT
range 155.5 - 166.6MHz. Q
REG
is a regenerated version
of the input clock.
- Mode 1: Q
OUT
range 622 - 666.5MHz. Q
REG
output 155.5-166.6MHz.
- Mode 2: Q
OUT
range 622 - 666.5MHz. Q
REG
is a regenerated version
of the input clock frequency.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
IDT5T940
DESCRIPTION:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
The three modes of output frequency range are controlled by the SELmode,
which is a 3-level pin. When SELmode is high or low, the Q
OUT
is a multiplied
version of the input clock while Q
REG
is a regenerated version of the input clock.
When SELmode is mid, the Q
OUT
is a multiplied version of the input clock while
Q
REG
is Q
OUT
/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLLBW
1
PLLBW
0
Q
REG
PLL
DIV
N
Q
REG
CLKIN
CLKIN
INPUT
MUX
Q
OUT
DIV
M
Q
OUT
REFIN
REFIN
LOCK,
FREQ.
DETECTOR
CONTROL
LOGIC
PD
LOCK
SEL
MODE
CLK/
REF
0
CLK/
REF
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
NOVEMBER 2004
DSC 6195/27

5T940-10NLGI8 Related Products

5T940-10NLGI8 0805F1000820JFR
Description PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28 Ceramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.000082uF, Surface Mount, 0805, CHIP, ROHS COMPLIANT
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
package instruction GREEN, PLASTIC, VFQFPN-28 , 0805
Reach Compliance Code unknown compliant
ECCN code EAR99 EAR99
JESD-609 code e3 e4
Number of terminals 28 2
Maximum operating temperature 85 °C 125 °C
Minimum operating temperature -40 °C -55 °C
Package shape SQUARE RECTANGULAR PACKAGE
surface mount YES YES
Terminal surface Matte Tin (Sn) - annealed Silver/Palladium (Ag/Pd)
s3c6410 clock system configuration
Could you please give me a 6410 clock configuration program, using PLL to configure the clock source ARMCLK=533M, PCLK=66M, thank you in advance....
ajungle ARM Technology
Problems with 50Hz and SPWM
Download (74.92 KB) 2010-10-10 10:54How to generate 50Hz square wave with SPWM...
SiangLiu stm32/stm8
C language header file nested include problem
As the title says, how do you handle and view the nested inclusion of C language header files? Nested inclusion is like ac including bh, bc including ah. I saw in the second edition of Modern Methods ...
白丁 Embedded System
Graduation Project of Dot Matrix Advertising Screen Based on Single Chip Microcomputer
I want to find a gunman to do a graduation project on a dot matrix advertising screen based on a single-chip microcomputer. If you are interested, please add QQ1210979462. The remuneration is negotiab...
雪莱 Embedded System
hehe
Artgoin is a paradise for art and a treasure house for art. People who love art should go there to have a look. You may find a rare treasure there....
cibgbvb Embedded System
ULINK2 Flat Cable Interface Summary
ULINK2 commonly has the following 5 types of flat cable interfaces:ARM 10-pin interface (1.27mm/0.05" pin spacing).ST 14-pin interface.OCDS 16-pin interface.ARM 20-pin interface (2.0mm/0.079" pin spac...
eeleader Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 590  2909  497  1535  707  12  59  10  31  15 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号