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GMC32X7R185F16NT

Description
Ceramic Capacitor, Multilayer, Ceramic, 16V, 1% +Tol, 1% -Tol, X7R, 15% TC, 1.8uF, Surface Mount, 1210, CHIP
CategoryPassive components    capacitor   
File Size434KB,22 Pages
ManufacturerCal-Chip Electronics
Environmental Compliance
Download Datasheet Parametric View All

GMC32X7R185F16NT Overview

Ceramic Capacitor, Multilayer, Ceramic, 16V, 1% +Tol, 1% -Tol, X7R, 15% TC, 1.8uF, Surface Mount, 1210, CHIP

GMC32X7R185F16NT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerCal-Chip Electronics
package instruction, 1210
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance1.8 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee3
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance1%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR, EMBOSSED PLASTIC, 7/13 INCH
positive tolerance1%
Rated (DC) voltage (URdc)16 V
size code1210
surface mountYES
Temperature characteristic codeX7R
Temperature Coefficient15% ppm/°C
Terminal surfaceMatte Tin (Sn) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
Base Number Matches1
Cal-Chip
Electronics, Incorporated
Multilayer Ceramic Chip Capacitors
Introduction
GMC S
ERIES
Multilayer Surface Mount Ceramic Capacitors are constructed by screen printing alternative layers of internal metallic
electrodes onto ceramic dielectric materials and firing into a concrete monolithic body, then completed by application of
metal end terminations which are fired to assure permanent bonding with the individual internal electrodes.
Multilayer ceramic capacitors have various features such as large capacitance values in small sizes and excellent high
frequency characteristics.
Moreover, chip capacitors can be used on surface mount assembly equipment. Our fully integrated manufacturing and
total quality control systems ensure unprecedented high standards of quality and reliability.
Chip Capacitor Selection
Selection of the most suitable capacitor for any application is based on the following:
Dielectric Type
The choice of dielectric is largely determined by the temperature stability required.
COG (NPO)
Capacitance change with temperature is 0-30ppm/°C which is less than -0.3%°C from -55°C to +125°C. Typical capacitance
change with life is less than -0.1% for NPOs, one-fifth that shown by most other dielectrics. NPO formulations show no aging
characteristics.
X7R/X5R
Its temperature variation of capacitance is within ±15% from -55°C to +125°C (-55°C to +85°C for X5R). The capacitance change is
non-linear.
Z5U
Despite their capacitance instability, Z5U formulations are very popular because of their small size, temperature range low
ESL, low ESR and excellent frequency response. These features are particularly important for decoupling application where
only a minimum capacitance value is required.
Y5V
Y5V formulations are for general purpose use in a limited temperature range. They have a wide temperature characteristic
of +22% - 82% capacitance change over the operating temperature range of -30°C to +85°C. Y5Vs high dielectric constant
allows the manufacture of very high capacitance values (up to 22MF) in small physical sizes.
Capacitance Value & Tolerance
Determined by circuit requirements. Note that chip prices decrease with lower capacitance value and looser tolerance.
Voltage
Determined by circuit requirements. Units are designed to exceed the withstanding voltage specification, i.e., the user need
not incorporate an additional safety margin.
Capacitor Size
Select the smallest unit permitted by the circuit constraints that provides the required capacitance and voltage rating.
All Cal-Chip capacitors conform to EIA specifications.
Capacitor Termination
Termination choice is largely determined by the chip attachment method. Silver-palladium is adequate for most applications
involving soldering or solder reflow.
Nickel barrier is standard and recommended for units exposed to repeated solder cycles, to minimize leaching of the ter-
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