CY39050V208-125BBC datasheet, PDF

Datasheet> All Categories > CY39050V208-125BBC

Preview

CY39050V208-125BBC: DescriptionCPLDs at FPGA Densities; File Size1MB，86 Pages; ManufacturerCypress Semiconductor

Download Datasheet View All

CY39050V208-125BBC Overview

CPLDs at FPGA Densities

Preview

Download Datasheet

View All

Delta39K™ ISR™

CPLD Family

CPLDs at FPGA Densities™

Features

• High density

— 30K to 200K usable gates

— 512 to 3072 macrocells

— 136 to 428 maximum I/O pins

— Twelve dedicated inputs including four clock pins,

four global I/O control signal pins and four JTAG

interface pins for boundary scan and reconfig-

urability

Embedded memory

— 80K to 480K bits embedded SRAM

• 16K to 96K bits of (dual-port) channel memory

High speed – 233-MHz in-system operation

AnyVolt™ interface

— 3.3V, 2.5V,1.8V, and 1.5V I/O capability

Low-power operation

— 0.18-mm six-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

— Standby current as low as 5mA

• Simple timing model

— No penalty for using full 16 product terms/macrocell

— No delay for single product term steering or sharing

• Flexible clocking

— Spread Aware™ PLL drives all four clock networks

• Allows 0.6% spread spectrum input clocks

• Several multiply, divide and phase shift options

— Four synchronous clock networks per device

— Locally generated product term clock

— Clock polarity control at each register

• Carry-chain logic for fast and efficient arithmetic opera-

tions

• Multiple I/O standards supported

— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-programmable Bus Hold capability on each I/O pin

• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,

rev. 2.2)

• CompactPCI hot swap ready

• Multiple package/pinout offering across all densities

— 208 to 676 pins in PQFP, BGA, and FBGA packages

— Simplifies design migration across density

— Self-Boot™ solution in BGA and FBGA packages

• In-System Reprogrammable™ (ISR™)

— JTAG-compliant on-board programming

— Design changes do not cause pinout changes

• IEEE1149.1 JTAG boundary scan

•

Development Software

•

Warp

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows



95/98/2000/XP™ and

Windows NT™ for $99

— Supports all Cypress programmable logic products

Delta39K™ ISR CPLD Family Members

Typical

Gates

[1]

16K – 48K

23K – 72K

46K – 144K

77K – 241K

92K – 288K

Cluster

memory

(Kbits)

192

320

384

Channel

memory

(Kbits)

Maximum

I/O Pins

174

218

302

386

428

MAX2

(MHz)

233

222

181

Speed-t

Pin-to-Pin

(ns)

7.2

7.5

8.5

Standby I

[2]

= 25°C

3.3/2.5V

5 mA

10 mA

20 mA

Device

39K30

39K50

39K100

39K165

39K200

Macrocells

512

768

1536

2560

3072

Notes:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I

values are with PLL not utilized, no output load and stable inputs.

Cypress Semiconductor Corporation

Document #: 38-03039 Rev. *H

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised August 1, 2003

Recommended Resources

Integrated switching regulated power supply circuit 01

Gantry milling machine regulated power supply schematic circuit

Radio frequency LCD display radio circuit diagram

TTL logic level controlled dual tracking regulated power supply

Count left pulse width multiplier

820e computer motherboard circuit diagram_39

Calculation of energy storage filter capacitor of series switching power supply Principle and design of switching power supply (Part 4): 1-2-4. Calculation of the energy storage filter capacitor of the series switching power supply We also start from the critical continuous current state of the current flowing through the energy storag...; noyisi112 Power technology

Performance of test systems in DC production testing of OLED displays: We have characterized the test speed, low current and low voltage measurement accuracy of a test system using four 2400s under a range of different measurement time intervals (i.e. different NPLC sett...; Jack_ma Test/Measurement

[Some tips for beginners] Library function operation flow of several commonly used peripheral modules: Haha, you don't need to read it, but beginners like me can read it.Library functions in GPIO operation flow 1. Core clock settingSysCtlClockSet 2. On-chip device clock enableSysCtlPeripheralEnable 3. ...; fishplj2000 Microcontroller MCU

Surface Acoustic Wave Filter: Overview of Surface Acoustic Waves Surface acoustic wave technology is an emerging field of science and technology that was developed in the late 1960s. It is a marginal discipline that combines acous...; fighting Analog electronics

[Question] Sensor Tile simulates USB flash drive problem: [i=s]This post was last edited by wbhb2011 on 2018-5-9 17:15[/i] The small expansion board of Sensor Tile with SD card is a good "data black box". So I want to simulate it into a USB flash drive, so t...; wbhb2011 ST Sensors & Low Power Wireless Technology Forum

Electronics Engineering Terminology: This is a good thing to share...; elephant Analog electronics

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components