A25L020/A25L010/A25L512 Series
2Mbit / 1Mbit /512Kbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
2Mbit /1Mbit /512Kbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB
Sectors
Revision History
Rev. No.
1.0
1.1
1.2
History
Initial issue
Add 8-pin TSSOP package type
Add the spec. of I
CC3
for 33MHz
Modify the I
CC1
and I
CC2
to 25μA
Modify the I
CC7
to 25mA
Modify the t
PP
to 3ms
Modify the t
SE
to 0.2s
Issue Date
February 27, 2008
September 2, 2008
January 9, 2009
Remark
Final
1.3
Modify the Sector Erase Time to 0.2S (typical)
Modify the Page Program Time to 2ms (typical)
Modify the Active Read Current to 35mA (Max.)
Modify the Program/Erase Current to 25mA (Max.)
Modify the Standby Current to 25μA (Max.)
Modify the t
BE
to 1.3s
Modify the t
CE
to 5s (A25L020)
Modify the t
CE
to 2.5s (A25L010)
Modify the t
CE
to 1.3s (A25L512)
(April, 2009, Version 1.3)
AMIC Technology Corp.
A25L020/A25L010/A25L512 Series
2Mbit / 1Mbit /512Kbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
FEATURES
Family of Serial Flash Memories
- A25L020: 2M-bit /256K-byte
- A25L010: 1M-bit /128K-byte
- A25L512: 512K-bit /64K-byte
Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 0.2s (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
Page Program (up to 256 Bytes) in 2ms (typical)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
100MHz Clock Rate (maximum)
Deep Power-down Mode 25µA (Max.)
Stand-by current 25µA (Max.)
Electronic Signatures
-
JEDEC Standard Two-Byte Signature
A25L020 (3012h)
A25L010 (3011h)
A25L512 (3010h)
-
RES Instruction, One-Byte, Signature, for backward
compatibility
A25L020 (11h)
A25L010 (10h)
A25L512 (05h)
Package options
-
8-pin SOP (150/209mil), 8-pin DIP (300mil) and 8-pin
TSSOP (A25L010V-F/A25L512V-F)
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L020/A25L010/A25L512 are 2M/1M/512K bit Serial
Flash Memory, with advanced write protection mechanisms,
accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The memory is organized as 4/2/1(A25L020/A25L010/A25L512)
blocks, each containing 16 sectors. Each sector is composed of
16 pages. Each page is 256 bytes wide. Thus, the whole
memory can be viewed as consisting of 1024/512/256
(A25L020/A25L010/A25L512) pages, or 262,144/131,072/
65,536 (A25L020/A25L010/A25L512) bytes.
The whole memory can be erased using the Chip Erase
instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
Pin Configurations
SOP8 Connections
A25L020/
A25L010/
A25L512
S
DO
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
DIO
S
DO
W
V
SS
DIP8 Connections
A25L020/
A25L010/
A25L512
1
2
3
4
8 V
CC
7 HOLD
6 C
5 DIO
TSSOP8 Connections
A25L010/
A25L512
S
DO
W
V
SS
1
2
3
4
8 V
CC
7 HOLD
6 C
5 DIO
(April, 2009, Version 1.3)
1
AMIC Technology Corp.
A25L020/A25L010/A25L512 Series
Block Diagram
HOLD
W
S
C
DIO
DO
I/O Shift Register
Control Logic
High Voltage
Generator
Address register
and Counter
256 Byte
Data Buffer
Status
Register
3FFFFh (2M),
1FFFFh (1M)
FFFFh (512K)
Y Decoder
Size of the
memory area
000FFh
00000h
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
DIO
DO
Serial Clock
Serial Data Input
1
Serial Data Output
2
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Description
Logic Symbol
V
CC
DIO
C
S
W
HOLD
A25L020/
A25L010/
A25L512
DO
S
W
HOLD
V
CC
V
SS
V
SS
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction is executed.
(April, 2009, Version 1.3)
2
AMIC Technology Corp.
A25L020/A25L010/A25L512 Series
SIGNAL DESCRIPTION
Serial Data Output (DO).
This output signal is used to
transfer data serially out of the device. Data is shifted out on
the falling edge of Serial Clock (C).
The DO pin is also used as an input pin when the Fast Read
Dual Input-Output instruction is executed.
Serial Data Input (DIO).
This input signal is used to transfer
data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
The DIO pin is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
Serial Clock (C).
This input signal provides the timing of the
serial interface. Instructions, addresses, or data present at
Serial Data Input (DIO) are latched on the rising edge of
Serial Clock (C). Data on Serial Data Output (DO) changes
after the falling edge of Serial Clock (C).
Chip Select (
S
).
When this input signal is High, the device
is deselected and Serial Data Output (DO) is at high
impedance. Unless an internal Program, Erase or Write
Status Register cycle is in progress, the device will be in the
Standby mode (this is not the Deep Power-down mode).
Driving Chip Select (
S
) Low enables the device, placing it in
the active power mode.
After Power-up, a falling edge on Chip Select (
S
) is required
prior to the start of any instruction.
Hold (
HOLD
).
The Hold (
HOLD
) signal is used to pause
any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DIO) and Serial
Clock (C) are Don’t Care. To start the Hold condition, the
device must be selected, with Chip Select (
S
) driven Low.
Write Protect (
W
).
The main purpose of this input signal is
to freeze the size of the area of memory that is protected
against program or erase instructions (as specified by the
values in the BP2, BP1, and BP0 bits of the Status Register).
(April, 2009, Version 1.3)
3
AMIC Technology Corp.
A25L020/A25L010/A25L512 Series
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Other)
SDO
SDI
SCK
C DO
DIO
C DO
DIO
C DO
DIO
SPI Memory
Device
CS3
CS2
CS1
S
W HOLD
SPI Memory
Device
SPI Memory
Device
S
W HOLD
S
W HOLD
Note: The Write Protect (
W
) and Hold (
HOLD
) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL
0
1
CPHA
0
1
C
C
DIO
DO
MSB
MSB
(April, 2009, Version 1.3)
4
AMIC Technology Corp.
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