DEMO MANUAL DC1370A
LTC2262-14/-12,
LTC2261-14/-12, LTC2260-14/-12, LTC2259-14/-12,
LTC2258-14/-12, LTC2257-14/-12, LTC2256-14/-12,
14-/12-Bit, 25Msps to 150Msps ADCs
DeScriPtion
Demonstration circuit 1370A supports a family of 14-/12-Bit
25Msps to 150Msps ADCs. Each assembly features one
of the following devices: LTC2262-14, LTC2262-12
LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12,
LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12,
LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, high
speed, high dynamic range ADCs.
Demonstration circuit 1370A supports the LTC2262 family
full rate CMOS, and DDR CMOS output mode. This family
of ADCs is also supported by demonstration circuit 1369,
which is compatible with DDR LVDS output modes.
Several versions of the 1370A demo board supporting the
LTC2262 14-/12-Bit series of A/D converters are listed in
Table 1. Depending on the required resolution and sample
rate, the DC1370A is supplied with the appropriate ADC.
The circuitry on the analog inputs is optimized for analog
input frequencies from 5MHz to 170MHz. Refer to the
data sheet for proper input networks for different input
frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and QuikEval and PScope are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Performance Summary
PARAMETER
Supply Voltage – DC1370A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (OV
DD
= 1.8V))
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
Convert Clock Level
Resolution
Input Frequency Range
SFDR
SNR
(T
A
= 25°C)
VALUE
Optimized for 3.6V
[3.5V
⇔
6.0V Min/Max]
1V
P-P
to 2V
P-P
1.3V
0.6V
1.750V (1.790V Typical)
0.050V (0.010V Typical)
0V to 3.6V
0.2V to 3.6V
CONDITIONS
Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 150mA
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Minimum High Level Output Voltage
Maximum Low Level Output Voltage
See Table 1
Single-Ended Encode Mode (ENC – Tied to GND)
Differential Encode Mode (ENC – Not Tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
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DEMO MANUAL DC1370A
Quick Start ProceDure
Table 1. DC1370A Variants
DC1370A VARIANTS
1370A-A
1370A-B
1370A-C
1370A-D
1370A-E
1370A-F
1370A-G
1370A-H
1370A-I
1370A-J
1370A-K
1370A-L
1370A-M
1370A-N
ADC PART NUMBER
LTC2261-14
LTC2260-14
LTC2259-14
LTC2258-14
LTC2257-14
LTC2256-14
LTC2261-12
LTC2260-12
LTC2259-12
LTC2258-12
LTC2257-12
LTC2256-12
LTC2262-14
LTC2262-12
RESOLUTION
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
14-Bit
12-Bit
MAXIMUM SAMPLE RATE
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
150Msps
150Msps
INPUT FREQUENCY
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
5MHz to 170MHz
Demonstration circuit 1370A is easy to set up to evaluate
the performance of the LTC2262 A/D converters. Refer to
Figure 1 for proper measurement equipment setup and
follow the procedure:
Setup
If a DC890 QuikEval™II Data Acquisition and Collection
System was supplied with the DC1370A demonstration
circuit, follow the DC890 Quick Start Guide to install the
required software and for connecting the DC890 to the
DC1370A and to a PC.
DC1370A Demonstration Circuit Board Jumpers
The DC1370A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP2: PAR/SER: Selects Parallel or Serial programming
mode. (Default - Serial)
JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle
Stabilizer. (Default - Enable)
JP4:
SHDN:
Enables and disables the LTC2262.
(Default - Enable)
Applying Power and Signals to the DC1370A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1370A,
the DC890 must FIRST be connected to a powered USB
port or provided an external 6V to 9V BEFORE applying
3.6V to 6.0V across the pins marked V
+
and GND on the
DC1370A. DC1370A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1370A demonstration circuit requires up
to 150mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an un-powered
hub, in which case it must be supplied an external 6V to
9V on turrets G7(+) and G1(–) or the adjacent 2.1mm
power jack.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 170MHz, refer to the LTC2262 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
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DEMO MANUAL DC1370A
Quick Start ProceDure
3.5V to 6V
+
JUMPERS ARE SHOWN IN
DEFAULT POSITIONS
ANALOG INPUT
N
PARALLEL DATA OUTPUT
TO DC890
PARALLEL/SERIAL
PROGRAMMING MODE
DUTY CYCLE
STABILIZER
SHDN
SINGLE ENDED
ENCODE CLOCK
Figure 1. DC1370A Setup
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR. In the
case of the DC1370A the bandpass filter used for the clock
should be used prior to the DC1075A.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1370A demonstration circuit board marked J7.
As a default the DC1370A is populated to have a single
ended input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075A that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2262 family.
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DEMO MANUAL DC1370A
Quick Start ProceDure
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. In the case of the DC1370A
a bandpass filter used for the clock should be used prior
to the DC1075A. Data sheet FFT plots are taken with 10
pole LC filters made by TTE (Los Angeles, CA) to suppress
signal generator harmonics, nonharmonically related spurs
and broadband noise. Low phase noise Agilent 8644B
generators are used with TTE bandpass filters for both
the clock input and the analog input.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1370A demonstration circuit board
marked J5 A
IN+
. These inputs are capacitive coupled to
balun transformers ETC1-1-13.
An internally generated conversion clock output is avail-
able on J1 which could be collected via a logic analyzer, or
other data collection system if populated with a SAMTEC
MEC8-150 type connector or collected by the DC890
QuikEval™II Data Acquisition Board using PScope™
software.
Software
The DC890 is controlled by the PScope System Software
provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC890
was provided, follow the DC890 Quick Start Guide and
the instructions below.
To start the data collection software if PScope.exe is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope Icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1370A demonstration circuit is properly connected
to the DC890, PScope should automatically detect the
DC1370A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to ADC Configuration....
Check the Config Manually box and use the following
configuration options, see Figure 2:
Figure 2. ADC Configuration
Manual Configuration settings:
Bits: 14 (or 12 for 12-bit parts)
Alignment: 14
FPGA Ld: CMOS
Channs: 2
Bipolar: Unchecked
Positive-Edge Clk: Checked
If everything is hooked up properly, powered and a suit-
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC890 Quick Start Guide and in
the online help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1370A board
serially through the DC890. There are several options
available in the LTC2262 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Board Options icon on the PScope toolbar (Figure 3).
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DEMO MANUAL DC1370A
Quick Start ProceDure
Clock Inversion:
Selects the polarity of the CLKOUT signal
• Normal (Default): Normal CLKOUT polarity
• Inverted: CLKOUT polarity is inverted
Figure 3. PScope Toolbar
Clock Delay:
Selects the phase delay of the CLKOUT signal:
• None (Default): No CLKOUT delay
• 45 deg: CLKOUT delayed by 45 degrees
• 90 deg: CLKOUT delayed by 90 degrees
• 135 deg: CLKOUT delayed by 135 degrees
Clock Duty Cycle:
Enable or disables Duty Cycle Stabilizer
• Stabilizer off (Default): Duty Cycle Stabilizer Disabled
• Stabilizer on: Duty Cycle Stabilizer Enabled
Output Current:
Selects the LVDS output drive current.
This option is not used on the DC1370A
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
This will bring up the menu shown in figure 4.
Figure 4. Demo Board Configuration Options
Internal Termination:
Enables LVDS Internal Termination.
This option is not used on the DC1370A
• Off (Default): Disables internal termination
• On: Enables internal termination
Outputs:
Enables Digital Outputs
• Enabled (Default): Enables digital outputs
• Disabled: Disables digital outputs
This menu allows any of the options available for the
LTC2262 family to be programmed serially. The LTC2262
family has the following options:
Power Control:
Selects between normal operation, nap,
and sleep modes
• Normal (Default): Entire ADC is powered, and active
• Nap: ADC core powers down while references stay active
• Shutdown: The entire ADC is powered down
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FPGA/CPLD
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