EEWORLDEEWORLDEEWORLD

Part Number

Search

CY39200Z256-83BGI

Description
CPLDs at FPGA Densities
File Size1MB,86 Pages
ManufacturerCypress Semiconductor
Download Datasheet View All

CY39200Z256-83BGI Overview

CPLDs at FPGA Densities

Delta39K™ ISR™
CPLD Family
CPLDs at FPGA Densities™
Features
• High density
— 30K to 200K usable gates
— 512 to 3072 macrocells
— 136 to 428 maximum I/O pins
— Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
Embedded memory
— 80K to 480K bits embedded SRAM
• 16K to 96K bits of (dual-port) channel memory
High speed – 233-MHz in-system operation
AnyVolt™ interface
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability
Low-power operation
— 0.18-mm six-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
— Standby current as low as 5mA
• Simple timing model
— No penalty for using full 16 product terms/macrocell
— No delay for single product term steering or sharing
• Flexible clocking
— Spread Aware™ PLL drives all four clock networks
• Allows 0.6% spread spectrum input clocks
• Several multiply, divide and phase shift options
— Four synchronous clock networks per device
— Locally generated product term clock
— Clock polarity control at each register
• Carry-chain logic for fast and efficient arithmetic opera-
tions
• Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-programmable Bus Hold capability on each I/O pin
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
• CompactPCI hot swap ready
• Multiple package/pinout offering across all densities
— 208 to 676 pins in PQFP, BGA, and FBGA packages
— Simplifies design migration across density
— Self-Boot™ solution in BGA and FBGA packages
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes do not cause pinout changes
• IEEE1149.1 JTAG boundary scan
Development Software
Warp
®
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows
95/98/2000/XP™ and
Windows NT™ for $99
— Supports all Cypress programmable logic products
Delta39K™ ISR CPLD Family Members
Typical
Gates
[1]
16K – 48K
23K – 72K
46K – 144K
77K – 241K
92K – 288K
Cluster
memory
(Kbits)
64
96
192
320
384
Channel
memory
(Kbits)
16
24
48
80
96
Maximum
I/O Pins
174
218
302
386
428
f
MAX2
(MHz)
233
233
222
181
181
Speed-t
PD
Pin-to-Pin
(ns)
7.2
7.2
7.5
8.5
8.5
Standby I
CC
[2]
T
A
= 25°C
3.3/2.5V
5 mA
5 mA
10 mA
20 mA
20 mA
Device
39K30
39K50
39K100
39K165
39K200
Macrocells
512
768
1536
2560
3072
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby I
CC
values are with PLL not utilized, no output load and stable inputs.
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. *H
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised August 1, 2003
FPGA
:Mad:...
出入茅庐 FPGA/CPLD
Discussion on the unsafe factors of access control intercom system
Driven by the progress of science and technology and people's demand for mobile communication services, building access control intercom systems are being applied to various communities. At present, t...
xyh_521 Industrial Control Electronics
A summary of many shared bicycle smart locks, very detailed!
[p=24, null, left][color=rgb(51, 51, 51)] According to the Trustdata mobile big data monitoring platform, as of the end of the second quarter of 2017, the top ten shared bicycles were: Mobike, ofo, Co...
fish001 Energy Infrastructure?
The time cost of spi reading and writing under linux. Help!!!
The board runs Linux. When I was adjusting SPI, I encountered a problem that the time overhead of reading and writing peripheral registers was too high. static void transfer (int fd) { int ret; uint8_...
agoodog Linux and Android
Please help me, I am using the msp430g2553 model, the display is LCD1602, but it just can't display numbers? ?
#include #include#define uchar unsigned char #define uintunsigned int#define RS_1 P2OUT |= 0X01 #define RS_0 P2OUT = ~0X01 #define RW_1 P2OUT |= 0X02 #define RW_0 P2OUT = ~0X02 #define E_1P2OUT |= 0X0...
fqh5455588 Microcontroller MCU
Digital mobile TV gradually becomes the new favorite of consumer electronics
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:01[/i]   "Mobile TV products are gradually becoming a hot spot in electronic consumption." At present, TCL has launched a mobile digita...
Mobile and portable

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1377  2026  2671  2124  1043  28  41  54  43  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号