CY3930V484-83BBI datasheet, PDF

Datasheet> All Categories > CY3930V484-83BBI

Preview

CY3930V484-83BBI: DescriptionCPLDs at FPGA Densities; File Size1MB，86 Pages; ManufacturerCypress Semiconductor

Download Datasheet View All

CY3930V484-83BBI Overview

CPLDs at FPGA Densities

Preview

Download Datasheet

View All

Delta39K™ ISR™

CPLD Family

CPLDs at FPGA Densities™

Features

• High density

— 30K to 200K usable gates

— 512 to 3072 macrocells

— 136 to 428 maximum I/O pins

— Twelve dedicated inputs including four clock pins,

four global I/O control signal pins and four JTAG

interface pins for boundary scan and reconfig-

urability

Embedded memory

— 80K to 480K bits embedded SRAM

• 16K to 96K bits of (dual-port) channel memory

High speed – 233-MHz in-system operation

AnyVolt™ interface

— 3.3V, 2.5V,1.8V, and 1.5V I/O capability

Low-power operation

— 0.18-mm six-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

— Standby current as low as 5mA

• Simple timing model

— No penalty for using full 16 product terms/macrocell

— No delay for single product term steering or sharing

• Flexible clocking

— Spread Aware™ PLL drives all four clock networks

• Allows 0.6% spread spectrum input clocks

• Several multiply, divide and phase shift options

— Four synchronous clock networks per device

— Locally generated product term clock

— Clock polarity control at each register

• Carry-chain logic for fast and efficient arithmetic opera-

tions

• Multiple I/O standards supported

— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-programmable Bus Hold capability on each I/O pin

• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,

rev. 2.2)

• CompactPCI hot swap ready

• Multiple package/pinout offering across all densities

— 208 to 676 pins in PQFP, BGA, and FBGA packages

— Simplifies design migration across density

— Self-Boot™ solution in BGA and FBGA packages

• In-System Reprogrammable™ (ISR™)

— JTAG-compliant on-board programming

— Design changes do not cause pinout changes

• IEEE1149.1 JTAG boundary scan

•

Development Software

•

Warp

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows



95/98/2000/XP™ and

Windows NT™ for $99

— Supports all Cypress programmable logic products

Delta39K™ ISR CPLD Family Members

Typical

Gates

[1]

16K – 48K

23K – 72K

46K – 144K

77K – 241K

92K – 288K

Cluster

memory

(Kbits)

192

320

384

Channel

memory

(Kbits)

Maximum

I/O Pins

174

218

302

386

428

MAX2

(MHz)

233

222

181

Speed-t

Pin-to-Pin

(ns)

7.2

7.5

8.5

Standby I

[2]

= 25°C

3.3/2.5V

5 mA

10 mA

20 mA

Device

39K30

39K50

39K100

39K165

39K200

Macrocells

512

768

1536

2560

3072

Notes:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I

values are with PLL not utilized, no output load and stable inputs.

Cypress Semiconductor Corporation

Document #: 38-03039 Rev. *H

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised August 1, 2003

Recommended Resources

Multi-pole leakage protector circuit b

STK4152 II power amplifier circuit diagram

Filter circuit diagram for converting square wave to sine wave

810 computer motherboard circuit diagram_26

Telephone intercom circuit

[Repost] Porting mplayer to Xunwei itop4412 development board: [align=left][color=rgb(51, 51, 51)][font=宋体][size=14pt]Reposted from Xunwei Development Board Forum: [/size][/font][/color][color=rgb(0, 0, 255)][font=宋体][size=14pt]http://www.topeetboard.com[/size][/...; Chihiro ARM Technology

【RPi PICO】Read the internal temperature sensor: Like other MCUs, the RP2040 has an internal temperature sensor that uses channel 4 of the ADC, but the value read is not the temperature, but needs to be converted.Temperature calculation formula: tem...; dcexpert MicroPython Open Source section

You have a live broadcast invitation - PCIe Gen5 and CXL solutions based on Intel Agilex FPGA: From the edge to the network core to the data center, all markets are undergoing rapid changes, so all industries must achieve large-scale innovation at an unprecedented speed. Intel Agilex FPGA is wi...; EEWORLD社区 FPGA/CPLD

am335x evm rtc power supply problem: Hello everyone, may I ask how the RTC module of AM335x EVM is powered? I have modified the time, but it will return to the original time as soon as the power is turned off. I use the Linux system and ...; maomaotu DSP and ARM Processors

Urgent help for the algorithm of this 51 single chip microcomputer: It was just delivered at noon today and I need it tomorrow. I am so worried now.I would like to ask all the experts to analyze the algorithm block diagram of this design. Thank you in advance.Things a...; hutong_200 51mcu

[Energia Development Environment] MSP430 LAUNCHPAD Study Notes 6--Angular Displacement Sensor: [i=s]This post was last edited by qinkaiabc on 2014-1-2 20:25[/i] [align=left][Energia Development Environment] MSP430 LAUNCHPAD Study Notes 6--Angular Displacement Sensor-Angle Measurement[/align] [a...; qinkaiabc Microcontroller MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components