EEWORLDEEWORLDEEWORLD

Part Number

Search

CY3930V676-125BBI

Description
CPLDs at FPGA Densities
File Size1MB,86 Pages
ManufacturerCypress Semiconductor
Download Datasheet View All

CY3930V676-125BBI Overview

CPLDs at FPGA Densities

Delta39K™ ISR™
CPLD Family
CPLDs at FPGA Densities™
Features
• High density
— 30K to 200K usable gates
— 512 to 3072 macrocells
— 136 to 428 maximum I/O pins
— Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
Embedded memory
— 80K to 480K bits embedded SRAM
• 16K to 96K bits of (dual-port) channel memory
High speed – 233-MHz in-system operation
AnyVolt™ interface
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability
Low-power operation
— 0.18-mm six-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
— Standby current as low as 5mA
• Simple timing model
— No penalty for using full 16 product terms/macrocell
— No delay for single product term steering or sharing
• Flexible clocking
— Spread Aware™ PLL drives all four clock networks
• Allows 0.6% spread spectrum input clocks
• Several multiply, divide and phase shift options
— Four synchronous clock networks per device
— Locally generated product term clock
— Clock polarity control at each register
• Carry-chain logic for fast and efficient arithmetic opera-
tions
• Multiple I/O standards supported
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-programmable Bus Hold capability on each I/O pin
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
• CompactPCI hot swap ready
• Multiple package/pinout offering across all densities
— 208 to 676 pins in PQFP, BGA, and FBGA packages
— Simplifies design migration across density
— Self-Boot™ solution in BGA and FBGA packages
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board programming
— Design changes do not cause pinout changes
• IEEE1149.1 JTAG boundary scan
Development Software
Warp
®
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows
95/98/2000/XP™ and
Windows NT™ for $99
— Supports all Cypress programmable logic products
Delta39K™ ISR CPLD Family Members
Typical
Gates
[1]
16K – 48K
23K – 72K
46K – 144K
77K – 241K
92K – 288K
Cluster
memory
(Kbits)
64
96
192
320
384
Channel
memory
(Kbits)
16
24
48
80
96
Maximum
I/O Pins
174
218
302
386
428
f
MAX2
(MHz)
233
233
222
181
181
Speed-t
PD
Pin-to-Pin
(ns)
7.2
7.2
7.5
8.5
8.5
Standby I
CC
[2]
T
A
= 25°C
3.3/2.5V
5 mA
5 mA
10 mA
20 mA
20 mA
Device
39K30
39K50
39K100
39K165
39K200
Macrocells
512
768
1536
2560
3072
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby I
CC
values are with PLL not utilized, no output load and stable inputs.
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. *H
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised August 1, 2003
stm32 systick always does not work, novice help
I'll post the code, please help me take a look, thanks in advance!main.c#include "main.h" GPIO_InitTypeDef GPIO_InitStructure; ErrorStatus HSEStartUpStatus;#define PC0_H GPIO_SetBits(GPIOC, GPIO_Pin_0...
zxz19890318 stm32/stm8
LPC1754 IAP program does not run in HyperTerminal? ? ?
I recently did an IAP upgrade, but I always felt that the program was downloaded (address starting from 0x10000), but the new program just wouldn't run. I posted the location where the Flash was writt...
BigLee1986 NXP MCU
★★Academic journal invitation letter
★★ Academic Journal Invitation Letter★ Domestic and foreign openly issued journals, semi-monthly, double issue, can publish papers on architecture, municipal administration, electronics, economy, tech...
whj110 Talking
Connect to high-speed ADC via SPI
...
至芯科技FPGA大牛 FPGA/CPLD
Detailed explanation of MSP430 crystal oscillator configuration
Compared with MSP430 (F149), MSP430 (F5529) is more powerful. Introduction to UCS The UCS of MSP430F5XX/MSP430F6XX series devices contains five clock sources, namely: XT1CLK, VLOCLK, REFOCLK, DCOCLK a...
fish001 Microcontroller MCU
Is there any PWM chip that can adjust the phase?
My requirement is to have two PWM pulses with the same period but different pulse widths. They have a front-to-back relationship when working, with A in front and B in the back, and the interval can b...
bigbat Motor Drive Control(Motor Control)

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 418  1393  1786  117  2401  9  29  36  3  49 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号