K7P403622M
K7P401822M
Document Title
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
128Kx36 & 256Kx18 SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 0.1
History
- Preliminary specification release
- Change specification format.
No change was made in parameters.
- Updated I
DD
, I
SB
and Input High Level.
Updated t
KHKL
, t
KLKH
, t
KHQX
, t
KHQX1
and AC Test Conditions.
For JTAG, updated Vendor Definition and added t
SVCH
/t
CHSX.
- Final specification release
Draft Date
Remark
Preliminary
April, 1997
Preliminary
Rev. 0.2
Jan. 1998
Preliminary
Rev. 1.0
Dec. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Rev 1.0
Dec. 1998
K7P403622M
K7P401822M
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
128Kx36 or 256Kx18 Organizations.
3.3V Core Power Supply.
LVTTL Input and Output Levels.
Differential, PECL Clock Inputs K, K.
Synchronous Read and Write Operation
Registered Input and Registered Output
Internal Pipeline Latches to Support Late Write.
Byte Write Capability(four byte write selects, one for each 9bits)
Synchronous or Asynchronous Output Enable.
Power Down Mode via ZZ Signal.
JTAG 1149.1 Compatible Test Access port.
119(7x17)Pin Ball Grid Array Package(14mmx22mm)
Organization
Part Number
K7P403622M-H20
128Kx36
K7P403622M-H16
K7P403622M-H19
K7P401822M-H20
256Kx18
K7P401822M-H16
K7P401822M-H19
Cycle
Time
5
6
7
5
6
7
Access
Time
2.5
3.0
3.5
2.5
3.0
3.5
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17]
CK
SS
SW
Latch
SWx
Register
SWx
Register
Latch
SW
Register
SW
Register
Read
Address
Register
1
Write
Address
Register
0
Row Decoder
128Kx36
or
256Kx18
Array
Column Decoder
Write/Read Circuit
SWx
(x=a, b, c, d)
or (x=a, b)
0
1
Data In
Register
SS
Register
SS
Register
Data Out
Register
G
ZZ
K
K
CK
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
V
DD
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Pin Name
V
DDQ
M
1
, M
2
G
SS
TCK
TMS
TDI
TDO
V
SS
NC
Pin Description
Output Power Supply
Read Protocol Mode Pins ( M
1
=V
SS
, M
2
=V
DD
)
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
GND
No Connection
-2-
Rev 1.0
Dec. 1998
K7P403622M
K7P401822M
PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7P403622M(128Kx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQc
8
DQc
6
V
DDQ
DQc
3
DQc
1
V
DDQ
DQd
1
DQd
3
V
DDQ
DQd
6
DQd
8
NC
NC
V
DDQ
2
SA
13
NC
SA
12
DQc
9
DQc
7
DQc
5
DQc
4
DQc
2
V
DD
DQd
2
DQd
4
DQd
5
DQd
7
DQd
9
SA
15
NC
TMS
3
SA
10
SA
9
SA
11
V
SS
V
SS
V
SS
SWc
V
SS
NC
V
SS
SWd
V
SS
V
SS
V
SS
M
1
SA
14
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
16
SA
0
V
DD
SA
1
TCK
128Kx36 & 256Kx18 SRAM
5
SA
7
SA
8
SA
6
V
SS
V
SS
V
SS
SWb
V
SS
NC
V
SS
SWa
V
SS
V
SS
V
SS
M
2
SA
3
TDO
6
SA
4
NC
SA
5
DQb
9
DQb
7
DQb
5
DQb
4
DQb
2
V
DD
DQa
2
DQa
4
DQa
5
DQa
7
DQa
9
SA
2
NC
NC
7
V
DDQ
NC
NC
DQb
8
DQb
6
V
DDQ
DQb
3
DQb
1
V
DDQ
DQa
1
DQa
3
V
DDQ
DQa
6
DQa
8
NC
ZZ
V
DDQ
K7P401822M(256Kx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQb
1
NC
V
DDQ
NC
DQb
4
V
DDQ
NC
DQb
6
V
DDQ
DQb
8
NC
NC
NC
V
DDQ
2
SA
13
NC
SA
12
NC
DQb
2
NC
DQb
3
NC
V
DD
DQb
5
NC
DQb
7
NC
DQb
9
SA
15
SA
17
TMS
3
SA
10
SA
9
SA
11
V
SS
V
SS
V
SS
SWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
M
1
SA
14
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
16
SA
1
V
DD
NC
TCK
5
SA
7
SA
8
SA
6
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
SWa
V
SS
V
SS
V
SS
M
2
SA
3
TDO
6
SA
4
NC
SA
5
DQa
9
NC
DQa
7
NC
DQa
5
V
DD
NC
DQa
3
NC
DQa
2
NC
SA
2
SA
0
NC
7
V
DDQ
NC
NC
NC
DQa
8
V
DDQ
DQa
6
NC
V
DDQ
DQa
4
NC
V
DDQ
NC
DQa
1
NC
ZZ
V
DDQ
-3-
Rev 1.0
Dec. 1998
K7P403622M
K7P401822M
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 SRAM
The K7P403622M and K7P401822M are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36
bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential PECL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are
updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second-
edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this
cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,
one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the
same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to
be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address
is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Low Power Dissipation Mode
During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the
SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be pre-
served and a recovery time(t
ZZR
) is required before the SRAM resumes to normal operation.
TRUTH TABLE
K
X
X
↑
↑
↑
↑
↑
↑
↑
↑
ZZ
H
L
L
L
L
L
L
L
L
L
G
X
H
L
L
X
X
X
X
X
X
SS
X
X
H
L
L
L
L
L
L
L
SW
X
X
X
H
L
L
L
L
L
L
SWa
X
X
X
X
H
L
H
H
H
L
SWb
X
X
X
X
H
H
L
H
H
L
SWc
X
X
X
X
H
H
H
L
H
L
SWd
X
X
X
X
H
H
H
H
L
L
DQa
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
IN
DQb
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
D
IN
DQc
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
Hi-Z
Hi-Z
D
IN
Hi-Z
D
IN
DQd
Hi-Z
Hi-Z
Hi-Z
Operation
Power Down Mode. No Operation
Output Disabled.
Output Disabled. No Operation
D
OUT
Read Cycle
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
IN
D
IN
No Bytes Written
Write first byte
Write second byte
Write third byte
Write fourth byte
Write all byte
-4-
Rev 1.0
Dec. 1998
K7P403622M
K7P401822M
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to V
SS
Output Supply Voltage Relative to V
SS
Voltage on any I/O pin Relative to V
SS
Maximum Power Dissipation
Output Short-Circuit Current
Operating Temperature
Storage Temperature
Symbol
V
DD
V
DDQ
V
TERM
P
D
I
OUT
T
OPR
T
STG
128Kx36 & 256Kx18 SRAM
Value
-0.5 to 3.9
V
DD
-0.5 to V
DD
+0.5
3
25
0 to 70
-55 to 125
Unit
V
V
V
W
mA
°C
°C
Note
NOTE
: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Input Low Level
PECL Clock Input High Level
PECL Clock Input Low Level
Operating Junction Temperature
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
IH
-PECL
V
IL
-PECL
T
J
Min
3.15
2.35
1.7
-0.3
2.135
1.490
10
Typ
3.3
2.5
-
-
-
-
-
Max
3.45
3.45
V
DD
+0.3
0.7
2.420
1.825
110
Unit
V
V
V
V
V
V
°C
Note
DC CHARACTERISTICS
Parameter
Average Power Supply Operating Current-x36
(V
IN
=V
IH
or V
IL
, ZZ & SS=V
IL
)
Symbol
I
DD5
I
DD6
I
DD7
I
DD5
I
DD6
I
DD7
Min
-
Max
650
600
550
600
550
500
60
1
1
V
DDQ
0.4
Unit
mA
Note
1, 2
Average Power Supply Operating Current-x18
(V
IN
=V
IH
or V
IL
, ZZ & SS=V
IL
)
Power Supply Standby Current
(V
IN
=V
IH
or V
IL
, ZZ=V
IH
)
Input Leakage Current
(V
IN
=V
SS
or V
DD
)
Output Leakage Current
(V
OUT
=V
SS
or V
DDQ
, ZZ=V
IH
, G=V
IH
)
Output High Voltage(I
OH
=-4mA) for V
DDQ
=3.3V
Output High Voltage(I
OH
=-4mA) for V
DDQ
=2.5V
Output Low Voltage(I
OL
=4mA)
NOTE
:1. Minimum cycle. I
OUT
=0mA.
2. 50% read cycles.
-
mA
1, 2
I
SB
I
LI
I
LO
V
OH1
V
OH2
V
OL
-
-1
-1
2.4
2.0
V
SS
mA
µA
µA
V
V
1
-5-
Rev 1.0
Dec. 1998
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