Standard Products
UT54ACTQ16245
RadHard CMOS 16-bit Bidirectional Transceiver, TTL Inputs, and
Three-State Outputs
Datasheet
May 16, 2012
www.aeroflex.com/radhard
FEATURES
16 non-inverting bidirectional buffers with three-state out-
puts
Guaranteed simultaneously switching noise level and
dynamic threshold performance
Separate control logic for each byte
0.6m Commercial RadHard CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
High speed, low power consumption
Output source/sink 24mA
Standard Microcircuit Drawing 5962-06244
- QML compliant part
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACTQ16245 transceiver is built using
Aeroflex’s Commercial RadHard
TM
epitaxial CMOS technol-
ogy and is ideal for space applications. This high speed, low
power UT54ACTQ16245 transceiver is designed to perform
asynchronous two-way communication and signal buffering.
Balanced outputs and low "on" output impedance make the
UT54ACTQ16245 well suited for driving high capacitance
loads and low impedance backplanes. The Transmit/Receive
input (T/R) controls the direction of data flow through the de-
vice. The output enable input (OEn, active low) overrides the
direction control (T/R) and disables both the A and B ports by
placing them in a high impedance state. These signals can be
driven from either port A or B. The direction and output enable
controls operate these devices as either two independent 8-bit
transceivers or one 16-bit transceiver
TM
LOGIC SYMBOL
OE1 (48)
OE2 (25)
(1)
T/R1
(47)
(46)
(44)
G1
G2
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
11
12
(24)
T/R2
A0
A1
A2
(2)
(3)
(5)
(6)
(8)
B0
B1
B2
B3
(43)
A3
(41)
A4
(40)
A5
(38)
A6
(37)
A7
(36)
A8
A9
A10
(35)
(33)
21
22
B4
(9)
B5
(11)
B6
(12)
B7
(13)
B8
(14)
B9
(16)
B10
(17)
B11
(19)
B12
(20)
B13
(22)
B14
(23)
B15
(32)
A11
(30)
A12
(29)
A13
(27)
A14
(26)
A15
PIN DESCRIPTION
Pin Names
OEn
T/Rn
A0-A15
B0-B15
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs
Side B Inputs or 3-State Outputs
FUNCTION TABLE
ENABLE
OEn
L
L
H
DIRECTION
T/Rn
L
H
X
OPERATION
B Data To A Bus
A Data To B Bus
Isolation, High-Z State on
Bus A and Bus B
1
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER
Total Dose
SEL Latchup
SEU Onset Let
Neutron Fluence
2
LIMIT
1.0E5
>108
N/A
3
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits V
DD
= 5.5V, T = 125
o
C.
2. Not tested, inherent of CMOS technology.
3. This device contains no memory storage elements which can be upset.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O
V
DD
T
STG
T
J
JC
I
I
P
D
PARAMETER
Voltage any pin during operation
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD
+.3
-0.3 to 6.0
-65 to +150
+175
20
10
310
UNITS
V
V
C
C
C/W
mA
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
t
INRISE
t
INFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Maximum input rise or fall time
(V
IN
transitioning between V
IL
(max) and V
IH
(min))
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
20
UNITS
V
V
C
ns
4
DC ELECTRICAL CHARACTERISTICS
1
( -55C < T
C
< +125C)
SYMBOL
V
IL
V
IH
I
IN
PARAMETER
Low level input voltage
2
High level input voltage
2
Input leakage current
CONDITION
V
DD
from 4.5V to 5.5V
V
DD
from 4.5 V to 5.5V
V
DD
from 4.5V to 5.5V
V
IN
= V
DD
or V
SS
I
OZ
Three-state output leakage current
V
DD
from 4.5V to 5.5V
V
IN
= V
DD
or V
SS
I
OS
Short-circuit output current
3,4
V
O
= V
DD
or V
SS
V
DD
from 4.5V to 5.5V
V
OL1
Low-level output voltage
5
I
OL
= 24mA
I
OL
= 24mA
I
OL
= 100A
V
IN
= 2.0V or 0.8V
V
DD
= 4.5V to 5.5V
V
OL2
Low-level output voltage
5,6
I
OL
= 50 mA
V
IN
= 2.0V or 0.8V
V
DD
= 5.5V
V
OH1
High-level output voltage
5
I
OH
= -24 mA
I
OL
= -24mA
I
OH
= -100A
V
IN
= 2.0V or 0.8V
V
DD
= 4.5V to 5.5V
V
OH2
High-level output voltage
5, 6
I
OH
= -50 mA
V
IN
= 2.0V or 0.8V
V
DD
= 5.5V
V
IC
+
Positive input clamp voltage
+125C
V
DD
- 1.3
0.4
1.5
V
-55C, 25C
V
DD
- 1.1
V
-55C, 25C
+125C
V
DD
- 0.64
V
DD
- 0.8
V
DD
- 0.2
V
-55C, 25C
+125C
0.8
1.0
V
-55C, 25C
+125C
0.35
0.5
0.2
V
-600
600
mA
-10
10
A
2.0
-1
1
MIN
MAX
0.8
UNIT
V
V
A
For input under test, I
IN
= 18mA
V
DD
= 0.0V
V
IC
-
Negative input clamp voltage
For input under test, I
IN
= -18mA
V
DD
= open
-1.5
-0.4
V
P
total
Power dissipation
7, 8, 9
C
L
= 20pF
V
DD
from 4.5V to 5.5V
5
1.5
mW/MHz
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