Product Specification
PE4270
Product Description
The PE4270 is a is a high-isolation Switch designed for CATV
applications, covering a broad frequency range from 1 to 3000
MHz. This single-supply SPST switch offers a single-pin
CMOS control interface with industry leading CTB
performance. It also provides low insertion loss, high isolation
and extremely low bias requirements while operating on a
single 3-volt supply. In a typical CATV application, the PE4270
provides for a cost effective and manufacturable solution vs.
mechanical relays.
The PE4270 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
Peregrine Specification 71/0010
RF1
ESD
ESD
SPST CATV UltraCMOS™ Switch
1 - 3000 MHz
Features
•
Integrated 0.25 watt terminations
•
CTB performance of 90 dBc
•
High isolation: 90 dB at 5 MHz, 63 dB
at 1000 MHz
•
Low insertion loss: 0.5 dB at 50 MHz,
0.70 dB at 1000 MHz
•
High input IP2: >80 dBm
•
CMOS/TTL single-pin control
•
Single +3-volt supply operation
•
Extremely low bias: 8
µA
@ 3 V
•
Available in a 6-lead DFN package
Figure 2. Package Type
6-lead DFN
RF2
75Ω
CMOS
Control
Driver
75Ω
CTRL
Table 1. Electrical Specifications @ +25 °C
(Z
S
= Z
L
= 75
Ω
)
Parameter
Operating Frequency
Insertion Loss
Isolation
Return Loss
1 dB Compression
CTB / CSO
Input IP2
Input IP3
2
2
3
2,4
1
Condition
1 – 50 MHz
1000 MHz
1 – 50 MHz
1000 MHz
5 - 1000 MHz,
V
CTRL
= 3.0V
1000 MHz
77 & 110 channels;
PO = 44 dBmV
1000 MHz
1000 MHz
Minimum
1
Typical
0.50
0.70
Maximum
3000
0.65
0.85
Units
MHz
dB
dB
dB
dBm
dBc
dBm
dBm
85
60
15
28
90
63
16
30
-90
80
50
15
2
Video Feedthrough
Switching Time
mV
pp
µS
Notes: 1. Device linearity will begin to degrade below 1 MHz.
2. Measured in a 50
Ω
system.
3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
4. Note Absolute Maximum ratings in Table 3.
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PE4270
Product Specification
Figure 3. Pin Configuration
V
DD
GND
RF1
1
2
3
Exposed
Solder Pad
(bottom side)
Table 4. Operating Ranges
Parameter
Min
2.7
Typ
3.0
8
Max
3.3
20
85
5
0.3xV
DD
Unit
V
µA
°C
V
V
6
5
4
RF2
GND
V
DD
Power Supply
I
DD
Power Supply Current
(V
DD
= 3V, V
CTRL
= 3V)
T
OP
Operating temperature
Control Voltage High
Control Voltage Low
-40
0.7xV
DD
0
CTRL
Table 5. Control Logic Truth Table
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
Control Voltage (CTRL)
High
1
Signal Path (RF1 to RF2)
ON
OFF
Pin Name
V
DD
GND
RF1
CTRL
GND
RF2
Description
Nominal 3 V supply connection.
Ground connection.
2
RF port.
1
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
Ground connection.
3
RF port.
1
Low
Notes: 1.
CTRL accepts both CMOS and TTL voltage leads.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Device Description
The
PE4270
high isolation SPST CATV Switch is
designed to support CATV applications such as
premise disconnect of a CATV signal path. This
function is typically performed by bulky and
expensive mechanical relays. The high isolation
characteristics, high compression point, and
integrated 75-ohm terminations make the
PE4270
an ideal, cost effective and manufacturable
product of choice.
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Document No. 70-0148-06
│
UltraCMOS™ RFIC Solutions
Notes: 1. Both RF pins must be held at 0 V
DC
or require external DC
blocking capacitors
2. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
P
IN
V
ESD
Parameter/Condition
Power supply voltage
Voltage on CTRL input
Storage temperature
Input power (50
Ω),
CTRL=1/CTRL=0
ESD voltage
(Human Body Model)
Min
-0.3
-0.3
-65
Max
4.0
5.5
150
33/24
500
Unit
V
V
°C
dBm
V
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE4270 in the 6-lead 3x3 DFN package is MSL1.
©2005-2010 Peregrine Semiconductor Corp. All rights reserved.
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PE4270
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted)
(75
Ω
impedance except as indicated)
Figure 4. Insertion Loss - RF1 to RF2
Figure 5. 1dB Compression & 3
rd
Order
Intercept Point (T = 25°C)
Figure 6. Isolation - RF1 to RF2
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PE4270
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless Otherwise Noted)
(75-ohm impedance)
Figure 7. RF1 Return Loss (Switch = ON)
Figure 8. RF1 Return Loss (Switch = OFF)
Figure 9. RF2 Return Loss (Switch = ON)
Figure 10. RF2 Return Loss (Switch = OFF)
©2005-2010 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0148-06
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UltraCMOS™ RFIC Solutions
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4270
Product Specification
Evaluation Kit
The
PE4270
EK board was designed to ease
customer evaluation of Peregrine’s high
performance SPST CATV MOSFET switch. RF1
is connected through a 75
Ω
transmission line via
the top left F connector, J1. RF2 is connected
through a 75
Ω
transmission line via the top right
F connector, J2. A 75
Ω
through transmission line
is available via F connectors J3 and J4. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated. V
DD
is supplied via J6-2, while
the control logic voltage is supplied via J5-2. It is
the responsibility of the customer to determine
proper supply decoupling for their design
application. It has been observed that by
removing C1 and C2 from the evaluation board
has not shown to degrade RF performance.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide model with
trace width of 0.021”, trace gaps of 0.030”,
dielectric thickness of 0.028”, metal thickness of
0.0021” and
ε
r
of 4.6. Note that the predominate
mode for these transmission lines is coplanar
waveguide with a ground plane.
Figure 11. Evaluation Board Layouts
Peregrine Specification 101/0167 (with F connectors)
Figure 12. Evaluation Board Schematic
Peregrine Specification 102/0224
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