531DA707M000DG datasheet, PDF - EEWORLD Datasheet

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531DA707M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 707MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size112KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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531DA707M000DG Overview

CMOS/TTL Output Clock Oscillator, 707MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531DA707M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1596198733
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	6
Nominal operating frequency	707 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

531DA707M000DG Preview

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Z T O

1 . 4 GH

)

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications



SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

GND

CLK+

Si530 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

CLK–

GND

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.2 5/11

Si530/531

Si530/531

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Supply Voltage

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Supply Current

Output enabled

LVPECL

CML

LVDS

CMOS

Tristate mode

Output Enable (OE)

Min

2.97

2.25

1.71

—

0.75 x V

—

–40

Typ

3.3

2.5

1.8

111

—

Max

3.63

2.75

1.89

121

108

—

0.5

Units

ºC

Operating Temperature Range

Notes:

Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.

OE pin includes a 17 k pullup resistor to V

Table 2. CLK± Output Frequency Characteristics

Parameter

Nominal Frequency

1,2

Symbol

Test Condition

LVPECL/LVDS/CML

CMOS

Min

—

–7

–20

–50

Typ

—

±1.5

—

Max

945

160

—

+20

+50

±3

±10

Units

MHz

ppm

Initial Accuracy

Temperature Stability

1,3

Measured at +25 °C at time of

shipping

ppm

Aging

Frequency drift over first year

Frequency drift over 20 year

life

—

Notes:

See Section 3. "Ordering Information" on page 7 for further details.

Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

Selectable parameter specified by part number.

Time from powerup or tristate mode to f

Rev. 1.2

Si530/531

Table 2. CLK± Output Frequency Characteristics (Continued)

Parameter

Total Stability

Symbol

Test Condition

Temp stability = ±7 ppm

Temp stability = ±20 ppm

Temp stability = ±50 ppm

Min

—

Typ

—

Max

±20

±31.5

±61.5

Units

ppm

Powerup Time

OSC

Notes:

See Section 3. "Ordering Information" on page 7 for further details.

Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

Selectable parameter specified by part number.

Time from powerup or tristate mode to f

Table 3. CLK± Output Levels and Symmetry

Parameter

LVPECL Output Option

Symbol

Test Condition

mid-level

swing (diff)

swing (single-ended)

mid-level

swing (diff)

Min

– 1.42

1.1

0.55

1.125

0.5

Typ

—

Max

– 1.25

1.9

0.95

1.275

0.9

Units

—

1.20

0.7

LVDS Output Option

CML Output Option

2.5/3.3 V option mid-level

1.8 V option mid-level

2.5/3.3 V option swing (diff)

—

1.10

0.35

0.8 x V

– 1.30

– 0.36

1.50

0.425

—

1.90

0.50

1.8 V option swing (diff)

= 32 mA

CMOS Output Option

—

0.4

350

—

Rise/Fall time (20/80%)

LVPECL/LVDS/CML

CMOS with C

= 15 pF

Symmetry (duty cycle)

SYM

LVPECL:

(diff)

LVDS:

CMOS:

– 1.3 V

1.25 V (diff)

—

Notes:



to V

– 2.0 V.

term

= 100



(differential).

= 15 pF

Rev. 1.2

Si530/531

Table 4. CLK± Output Phase Jitter

Parameter

Phase Jitter (RMS)

for F

OUT

> 500 MHz

Phase Jitter (RMS)

for F

OUT

of 125 to 500 MHz

Phase Jitter (RMS)

for F

OUT

of 10 to 160 MHz

CMOS Output Only

Symbol

Test Condition

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

Min

—

Typ

0.25

0.26

0.36

0.34

0.62

0.61

Max

0.40

0.37

0.50

0.42

—

Units



12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

Notes:

Refer to AN256 for further information.

Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2 MHz for 10 MHz < FOUT <50 MHz.

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

PER

Test Condition

RMS

Peak-to-Peak

Min

—

Typ

Max

—

Units

*Note:

Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 6. CLK± Output Phase Noise (Typical)

Offset Frequency (f)

120.00 MHz

LVDS

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

100 MHz

–112

–122

–132

–137

–144

–150

n/a

156.25 MHz

LVPECL

–105

–122

–128

–135

–144

–147

n/a

622.08 MHz

LVPECL

–97

–107

–116

–121

–134

–146

–148

Units

dBc/Hz

Rev. 1.2

Si530/531

Table 7. Environmental Compliance

The Si530/531 meets the following qualification test requirements.

Parameter

Mechanical Shock

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL1

Gold over Nickel

Table 8. Absolute Maximum Ratings

Parameter

Maximum Operating Temperature

Supply Voltage, 1.8 V Option

Supply Voltage, 2.5/3.3 V Option

Input Voltage (any input pin)

Storage Temperature

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (Pb-free profile)

Soldering Temperature Time @ T

PEAK

(Pb-free profile)

Symbol

AMAX

ESD

PEAK

Rating

–0.5 to +1.9

–0.5 to +3.8

–0.5 to V

+ 0.3

–55 to +125

2500

260

20–40

Units

ºC

seconds

Notes:

Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO

for further information, including soldering profiles.

Rev. 1.2

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