PRELIMINARY
CY7C1001
CY7C1002
Features
D
D
D
D
D
D
D
D
High speed
t
AA
= 12 ns
Transparent write (7C1001)
CMOS for optimum speed/power
Low active power
910 mW
Low standby power
275 mW
2.0V data retention (optional)
100
µ
W
Automatic power down when
deselected
TTL compatible inputs and outputs
The CY7C1001 and CY7C1002 are high
performance CMOS static RAMs orga
nized as 262,144 x 4 bits with separate I/O.
Easy memory expansion is provided by ac
tive LOW chip enable (CE) and three
state drivers. Both devices have an auto
matic power down feature, reducing the
power consumption by more than 65%
when deselected.
Writing to the device is accomplished by
taking both chip enable (CE) and write en
able (WE) inputs LOW. Data on the four
input pins (I
0
through I
3
) is written into the
memory location specified on the address
pins (A
0
through A
17
).
Reading the device is accomplished by tak
ing chip enable (CE) LOW while write en
I
0
I
1
Functional Description
256K x 4 Static RAM
with Separate I/O
able (WE) remains HIGH. Under these
conditions, the contents of the memory lo
cation specified on the address pins will ap
pear on the four data output pins (O
0
through O
3
).
The data output pins on the CY7C1001
and the CY7C1002 are placed in a high
impedance state when the device is dese
lected (CE HIGH). The CY7C1002's out
puts are also placed in a high impedance
state during a write operation (CE and WE
LOW). In a write operation on the
CY7C1001, the output pins will carry the
same data as the inputs after a specified
delay.
The CY7C1001 and CY7C1002 are avail
able in standard 300 mil wide DIPs and
SOJs.
DIP/SOJ
Top View
Logic Block Diagram
Pin Configuration
I
2
I
3
NC
A
16
A
17
A
0
A
1
A
2
A
10
A
11
A
12
A
13
A
14
A
9
I
3
I
2
CE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7C1001
7C1002
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
3
A
4
A
5
A
6
A
7
A
8
NC
I
0
I
1
O
0
O
1
O
2
O
3
WE
C1001-2
INPUT BUFFER
A
2
A
3
A
4
A
5
A
6
A
7
A
8
SENSE AMPS
A
1
ROW DECODER
A
0
O
0
O
1
512 x 512 x 4
ARRAY
O
2
O
3
COLUMN
DECODER
POWER
DOWN
A
12
A
13
A
14
A
15
A
16
A
17
A
10
A
11
A
9
CE
7C1002 ONLY
WE
7C1001 ONLY
C1001-1
Selection Guide
7C1001-12
7C1001-15
7C1002-15
7C1001-20
7C1002-20
7C1001-25
7C1002-25
Maximum Access Time (ns)
Maximum Operating Current
7C1002-12
Commercial
Military
Maximum Standby Current (mA) Commercial
Military
Cypress Semiconductor Corporation
12
165
50
15
155
165
40
40
20
140
150
30
30
25
130
140
30
30
D
3901 North First Street
1
D
San Jose
D
CA 95134
D
408-943-2600
November 1991 - Revised April 1995
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . -65
_
C to +150
_
C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55
_
C to +125
_
C
Supply Voltage on V
CC
Relative to GND
[1]
. -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
. . . . . . . . . . . . . . . . . . -0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
. . . . . . . . . . . . . . . . -0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) . . . . . . . . . . . . . . . . . . . . . 20 mA
CY7C1001
CY7C1002
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MIL STD 883, Method 3015)
Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial
Military
Ambient
Temperature
[2]
0
_
C to + 70
_
C
-55
_
C to + 125
_
C
V
CC
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
[3]
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[1]
Test Conditions
V
CC
= Min.,
I
OH
= -4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
7C1001-12 7C1001-15 7C1001-20 7C1001-25
7C1002-12 7C1002-15 7C1002-20 7C1002-25
Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.4
0.4
2.2
-0.3
-1
-5
V
CC
+ 0.3
0.8
+1
+5
-300
2.2
-0.3
-1
-5
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
-300
155
165
50
40
40
2
2
2
2.2
-0.3
-1
-5
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
-300
140
150
30
30
2
2
2.2
-0.3
-1
-5
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
-300
130
140
30
30
2
2
mA
mA
V
V
V
V
Input Load Current GND < V
I
< V
CC
Output Leakage
Current
Output Short
Circuit Current
[4]
V
CC
Operating
Supply Current
Automatic CE
Power Down
Current
TTL Inputs
Automatic CE
Power Down
Current
C
t
CMOS Inputs
[5]
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.
,
I
OUT
= 0 mA
mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE > V
IH,
V
IN
> V
IH
or
V
IN
< V
IL
,
f = f
MAX
Max. V
CC
,
CE > V
CC
- 0.3V
,
V
IN
> V
CC
- 0.3V
0 3V
or V
IN
< 0.3V, f=0
Com'l
Mil
Com'l
Mil
Com'l
Mil
m
A
m
A
mA
mA
165
I
SB1
I
SB2
Capacitance
Parameter
Description
Input Capacitance
p
p
Output Capacitance
Test Conditions
T
A
= 25
_
C, f = 1 MHz,
,
,
V
CC
= 5.0V
5 0V
Max.
7
10
10
Unit
pF
pF
pF
C
IN
: Addresses
C
IN
: Controls
C
OUT
1.
2.
3.
Notes:
V
IL
(min.) = -2.0V for pulse durations of less than 20 ns.
T
A
is the instant on" case temperature.
See the last page of this specification for Group A subgroup testing in
formation.
4.
5.
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
2
PRELIMINARY
AC Test Loads and Waveforms
R1 480
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
CY7C1001
CY7C1002
W
R1 480
5V
OUTPUT
W
R2
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
255
W
JIG AND
SCOPE
5 pF
INCLUDING
255
W
GND
< 3 ns
< 3 ns
(a)
Equivalent to:
THÉVENIN EQUIVALENT
167
OUTPUT
(b)
C1001-3
C1001-4
W
1.73V
Switching Characteristics
Over the Operating Range
[3, 6]
7C1001-12
7C1002-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
0
12
3
6
0
15
3
12
3
7
0
20
12
12
3
15
3
8
0
25
15
15
3
20
3
10
20
20
3
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
7C1001-15
7C1002-15
Min.
Max.
7C1001-20
7C1002-20
Min.
Max.
7C1001-25
7C1002-25
Min.
Max.
Unit
Description
Min.
Max.
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
DWE
t
DCE
t
ADV
Write Cycle Time
CE LOW to Write End
Address Set Up to Write End
Address Hold from Write End
Address Set Up to Write Start
WE Pulse Width
Data Set Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[7, 8]
WE LOW to Data Valid (7C1001)
CE LOW to Data Valid (7C1001)
Data Valid to Output Valid (7C1001)
12
10
10
0
0
10
7
0
3
6
12
12
12
15
12
12
0
0
12
8
0
3
7
15
15
15
20
15
15
0
0
15
10
0
3
8
20
20
20
25
20
20
0
0
20
15
0
3
10
25
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing ref
erence levels of 1.5V input pulse levels of 0 to 3.0V and output loading
,
,
of the specified I
OL
/I
OH
and 30 pF load capacitance.
7.
8.
At any given temperature and voltage condition, t
HZCE
is less than
t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steady state voltage.
9.
The internal write time of the memory is defined by the overlap of CE
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input
data set up and hold timing should be referenced to the leading edge
of the signal that terminates the write.
3
PRELIMINARY
Data Retention Characteristics
CY7C1001
CY7C1002
Over the Operating Range (L Version Only)
Commercial
Military
Min.
Max.
Units
Parameters
Description
Conditions
[10]
Min.
Max.
V
DR
I
CCDR
t
CDR[5]
t
R[5]
Note:
V
CC
for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
V
CC
= V
DR
= 2.0V
,
CE > V
CC
- 0.3V
0 3V
,
V
IN
> V
CC
- 0.3V or
V
IN
< 0.3V
2.0
50
0
t
RC
2.0
70
0
t
RC
V
m
A
ns
ns
.
10. No input may exceed V
CC
+ 0.5V
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
4.5V
t
R
V
DR
> 2V
CE
C1001-5
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C1001-6
Read Cycle No. 2
[12, 13
]
ADDRESS
t
RC
CE
t
ACE
t
HZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
t
LZCE
t
PU
V
CC
SUPPLY
CURRENT
50%
50%
t
PD
DATA VALID
ICC
ISB
C1001-7
Notes:
11. Device is continuously selected, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
4
PRELIMINARY
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[9, 14]
t
WC
CY7C1001
CY7C1002
ADDRESS
t
SA
t
SCE
CE
t
AW
t
PWE
WE
t
HA
t
SD
DATA VALID
t
HD
DATA IN
DATA OUT
(7C1002)
HIGH IMPEDANCE
t
ADV
t
HZCE
DATA OUT
(7C1001)
t
LZCE
t
DCE
DATA VALID
C1001-8
Write Cycle No. 2 (WE Controlled)
[9]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
t
SD
DATA IN
DATA VALID
t
HD
t
HZWE
DATA OUT
(7C1002)
t
DWE
DATA OUT
(7C1001)
t
ADV
t
LZWE
HIGH IMPEDANCE
t
HZCE
DATA VALID
C1001-9
Note:
14. If CE goes HIGH simultaneously with WE going HIGH, the output
remains in a high impedance state (7C1002 only).
5
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