CY7C1327F
4-Mb (256K x 18) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 256K ×18 common I/O architecture
• 3.3V core power supply
• 3.3V / 2.5V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119 Ball
BGA packages.
• “ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
[A:B]
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1327F operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
MODE
ADDRESS
REGISTER
2
A[1:0]
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
WRITE REGISTER
DQ
B,
DQP
B
WRITE DRIVER
MEMORY
ARRAY
BW
A
BWE
GW
CE
1
CE2
CE3
OE
ENABLE
REGISTER
DQ
A,
DQP
A
WRITE REGISTER
DQ
A,
DQP
A
WRITE DRIVER
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com
Cypress Semiconductor Corporation
Document #: 38-05216 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised December 12, 2003
CY7C1327F
Selection Guide
250 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby
Current
2.6
325
40
225 MHz
2.6
290
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
100 MHz
4.5
205
40
Unit
ns
mA
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-pin TQFP
CY7C1327F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
Document #: 38-05216 Rev. *B
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 17
CY7C1327F
Pin Configurations
119-ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC
V
DDQ
2
A
CE
2
A
NC
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
A
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
V
ss
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
NC
NC
5
A
A
A
V
SS
V
SS
V
SS
V
ss
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
NC
DQ
A
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05216 Rev. *B
Page 3 of 17
CY7C1327F
Pin Definitions
Name
A
0
, A
1
, A
TQFP
37,36,
32,33,34,
35,44,45,
46,47,48,
49,50,80,
81,82,99,
100
93,94
88
BGA
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
C6,R6,T6
L5,G3
H4
I/O
Description
Input-
Address Inputs used to select one of the 256K address locations. Sampled
Synchronous at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and CE
3
are sampled active. A1, A0 feed the 2-bit counter.
BW
A,
BW
B
GW
Input-
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct
Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Global Write Enable Input, active LOW.
When asserted LOW on the
Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW
[A:B]
and BWE).
Input-
Byte Write Enable Input, active LOW.
Sampled on the rising edge of
Synchronous CLK. This signal must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input.
Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV is asserted LOW, during
a burst operation.
BWE
CLK
87
89
M4
K4
CE
1
CE
2
CE
3
98
E4
97
92
B2
B6
OE
86
F4
Input-
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP
is ignored if CE
1
is HIGH.
Input-
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE
1
and CE
3
to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE
1
and CE
2
to select/deselect the device. Not
connected for BGA. Where referenced, CE
3
is assumed active throughout
this document for BGA.
Input-
Output Enable, asynchronous input, active LOW.
Controls the
Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK, active
Synchronous
LOW.
When asserted, it automatically increments the address in a burst
cycle.
Input-
Address Strobe from Processor, sampled on the rising edge of CLK,
Synchronous
active LOW.
When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is
deasserted HIGH.
Input-
ZZ “sleep” Input, active HIGH.
This input, when High places the device
Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK,
Synchronous
active LOW.
When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
I/O-
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data
Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver
the data contained in the memory location specified by “A” during the
previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When
HIGH, DQs and DQP
[A:B]
are placed in a three-state condition.
ADV
83
G4
ADSP
84
A4
ZZ
64
T7
ADSC
85
B4
DQ
A,
DQ
B
DQP
A,
DQP
B
58,59,62,
63,68,69,
72,73
8,9,12,13,
18,19,22,
23
74,24
F6,H6,L6,
N6,E7,G7,
K7,P7
D1,H1,L1,
N1,E2,G2,
K2,M2,
D6,P2
Document #: 38-05216 Rev. *B
Page 4 of 17
CY7C1327F
Pin Definitions
(continued)
Name
V
DD
V
SS
TQFP
BGA
I/O
Description
15,41,65, J2,C4,J4,
91
R4,J6
5,10,17,
21,26,40,
55,60,67,
71,76,90
D3,E3,F3,
H3,K3,L3,
M3,N3,P3,
D5,E5,F5,
G5,H5,K5,
M5,N5,P5
Power Supply
Power supply inputs to the core of the device.
Ground
Ground for the device.
V
DDQ
4,11,20, A1,F1,J1,
27,54,61, M1,U1,A7,
70,77
F7,J7,M7,
U7
31
R3
I/O Ground
Ground for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order.
When tied to GND selects linear burst sequence.
When tied to V
DD
or left floating selects interleaved burst sequence. This
is a strap pin and should remain static during device operation. Mode Pin
has an internal pull-up.
No Connects.
Not internally connected to the die
NC
1,2,3,6,7,
14,16,25,
28,29,30,
38,39,42,
43,51,52,
53,56,57,
66,75,78,
79,95,96
B1,C1,E1,
G1,K1,P1,
R1,T1,D2,
F2,H2,L2,
N2,U2,J3,
U3,D4,L4,
T4,U4,J5,
U5,E6,G6,
K6,M6,P6,
U6,B7,C7,
D7,H7,L7,
N7,R5,R7
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1327F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:B]
) inputs. A Global Write
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the Write
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
1
is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single Read cycles are supported. Once the SRAM is
deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
1
, CE
2
, CE
3
are all asserted active. The address
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
[A:B]
) and
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
Document #: 38-05216 Rev. *B
Page 5 of 17
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