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EPSA12BBJA-30.720MTR

Description
CRYSTAL OSCILLATOR, CLOCK, 30.72 MHz, CMOS OUTPUT
CategoryPassive components    oscillator   
File Size788KB,10 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric View All

EPSA12BBJA-30.720MTR Overview

CRYSTAL OSCILLATOR, CLOCK, 30.72 MHz, CMOS OUTPUT

EPSA12BBJA-30.720MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid7039081506
Reach Compliance Codecompliant
Other featuresPOWER DOWN; ENABLE/DISABLE FUNCTION; TAPE AND REEL
maximum descent time3 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals4
Nominal operating frequency30.72 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load15 pF
physical size7.0mm x 5.0mm x 1.6mm
longest rise time3 ns
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Ecliptek | EPSA12 Series Oscillator
http://www.ecliptek.com/oscillators/EPSA12/
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| 714-433-1200 |
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EPSA12 Series Oscillator
Spread Spectrum Quartz Crystal Clock Oscillators LVCMOS (CMOS) 2.5Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount
(SMD)
2011/65 +
2015/863
168 SVHC
Revision B 08/29/2012
Electrical Specifications
Nominal Frequency
2.000MHz to 166.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability
(Inclusive of all conditions: Frequency Stability over the Operating
Temperature Range, Supply Voltage Change, Output Load Change,
First Year Aging at 25°C, Shock, and Vibration)
±50ppm Maximum
-40°C to +85°C
2.5V
DC
±5%
-0.5V
DC
to +3.2V
DC
15mA Maximum
18mA Maximum
22mA Maximum
25mA Maximum
166MHz
over
over
over
over
Nominal
Nominal
Nominal
Nominal
Frequency
Frequency
Frequency
Frequency
of
of
of
of
2MHz to 25MHz
25.000001MHz to 50MHz
50.000001MHz to 100MHz
100.000001MHz to
Operating Temperature Range
Supply Voltage (V
DD
)
Maximum Supply Voltage
Input Current
Output Voltage Logic High (V
OH
)
Output Voltage Logic Low (V
OL
)
Duty Cycle
90% of V
DD
Minimum (I
OH
= -8mA)
10% of V
DD
Maximum (I
OL
= +8mA)
Measured at 50% of waveform
50 ±5(%)
Measured at 10% to 90% of Waveform
3nSec Maximum
15pF Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
Power Down (Disabled Output: High Impedance)
70% of V
DD
Minimum or No Connection to Enable Output, 30% of V
DD
Maximum to Disable Output
70% of V
DD
Minimum or No Connection to Enable Output, 30% of V
DD
Maximum to Disable Output
100nSec Maximum
3mSec Maximum
Unloaded; Pad 1 = Ground
10 A Maximum (Power Down)
100nSec Maximum
Rise Time/Fall Time
Load Drive Capability
Output Logic Type
Output Control Function
Power Down Input Voltage (Vih and Vil)
Tri-State Input Voltage (Vih and Vil)
Power Down Output Disable Time
Power Down Output Enable Time
Standby Current
Tri-State Output Disable Time
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28-Jan-2016 2:05 PM

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