FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00001-8v0-E
Memory FRAM
16 K (2 K
×
8) Bit I
2
C
MB85RC16
■
DESCRIPTION
The MB85RC16 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 2,048 words
×
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile
memory cells.
Unlike SRAM, the MB85RC16 is able to retain data without using a data backup battery.
The memory cells used in the MB85RC16 have at least 10
12
Read/Write operation endurance per byte, which
is a significant improvement over the number of read and write operations supported by other nonvolatile
memory products.
The MB85RC16 can provide writing in one byte units because the long writing time is not required unlike
Flash memory and E
2
PROM. Therefore, the writing completion waiting sequence like a write busy state is
not required.
■
FEATURES
: 2,048 words
×
8 bits
: Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
: 1 MHz (Max)
: 10
12
times/byte
: 10 years (
+
85
°C),
95 years (
+
55
°C),
over 200 years (
+
35
°C)
: 2.7 V to 3.6 V
: Operating power supply current 70
μA
(Typ @1 MHz)
Standby current 0.1
μA
(Typ)
• Operation ambient temperature range :
−
40
°C
to
+
85
°C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
8-pin plastic SON (LCC-8P-M04)
RoHS compliant
•
•
•
•
•
•
•
Bit configuration
Two-wire serial interface
Operating frequency
Read/Write endurance
Data retention
Operating power supply voltage
Low power consumption
Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.2
MB85RC16
■
PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
NC
1
8
VDD
NC
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
NC
2
7
WP
NC
NC
VSS
NC
3
6
SCL
VSS
4
5
SDA
(FPT-8P-M02)
(LCC-8P-M04)
■
PIN FUNCTIONAL DESCRIPTIONS
Pin
Number
1 to 3
4
Pin Name
NC
VSS
Functional Description
No Connect pins
Leave these pins open, or connect to VDD or VSS.
Ground pin
Serial Data I/O pin
This is an I/O pin which performs bidirectional communication for both memory ad-
dress and writing/reading data. It is possible to connect multiple devices. It is an
open drain output, so a pull-up resistor is required to be connected to the external
circuit.
Serial Clock pin
This is a clock input pin for input/output timing serial data. Data is sampled on the
rising edge of the clock and output on the falling edge.
Write Protect pin
When the Write Protect pin is the “H” level, writing operation is disabled. When the
Write Protect pin is the “L” level, the entire memory region can be overwritten.
Reading operation is always enabled regardless of the Write Protect pin input level.
The write protect pin is internally pulled down to VSS pin, and that is recognized as
the “L” level (write enabled) when the pin is the open state.
Supply Voltage pin
5
SDA
6
SCL
7
WP
8
VDD
2
DS501-00001-8v0-E
MB85RC16
■
BLOCK DIAGRAM
Serial/Parallel Converter
SDA
Memory Address Counter
Row Decoder
FRAM Array
2,048
×
8
WP
Control circuit
SCL
Column Decoder/Sense Amp/
Write Amp
■
I
2
C (Inter-Integrated Circuit)
The MB85RC16 has the two-wire serial interface; the I
2
C bus, and operates as a slave device.
The I
2
C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, an I
2
C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration.
•
I
2
C Interface System Configuration Example
VDD
Pull-up Resistors
SCL
SDA
I
2
C Bus
Master
I
2
C Bus
MB85RC16
I
2
C Bus
Other slave
DS501-00001-8v0-E
3
MB85RC16
■
I
2
C COMMUNICATION PROTOCOL
The I
2
C bus provides communication by two wires only, therefore, the SDA input should change while SCL
is the “L” level. However, when starting and stopping the communication sequence, SDA is allowed to change
while SCL is the “H” level.
• Start Condition
To start read or write operations by the I
2
C bus, change the SDA input from the “H” level to the “L” level while
the SCL input is in the “H” level.
• Stop Condition
To stop the I
2
C bus communication, change the SDA input from the “L” level to the “H” level while the SCL
input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the
standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and
enters the standby state.
•
Start Condition, Stop Condition
SCL
SDA
“H” or “L”
Start
Stop
Note : At the write operation, the FRAM device does not need the memory programming wait time (t
WC
) after
issuing the Stop Condition.
4
DS501-00001-8v0-E
MB85RC16
■
ACKNOWLEDGE (ACK)
In the I
2
C bus, serial data including memory address or memory information is sent and received in units of
8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The
receiver side usually outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully
transmitted and received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this
9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z released period, the
receiver side pulls the SDA line down to indicate the “L” level that the previous 8 bits communication is
successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
•
Acknowledge timing overview diagram
SCL
1
2
3
8
9
SDA
The transmitter side should always release SDA on the 9th bit.
At this time, the receiver side outputs a pull-down if the
previous 8 bits data are received correctly (ACK response).
ACK
Start
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MEMORY ADDRESS STRUCTURE
The MB85RC16 has the memory address buffer to store the 11-bit information for the memory address.
As for byte write, page write and random read commands, the complete 11-bit memory address is configured
by inputting the memory upper address (3 bits) and the memory lower address (8 bits), and saved to the
memory address buffer. Then access to the memory is performed.
As for a current address read command, the complete 11-bit memory address is configured and saved to
the memory address buffer, by inputting the memory upper address (3 bits) and the memory lower address(8
bits) which has saved in the memory address buffer. Then access to the memory is performed.
DS501-00001-8v0-E
5
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