Solutions from IDT. The ICS8533I-31 has selectable
differential clock or crystal inputs. The CLK, nCLK pair can accept
most standard differential input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin.
Features
•
•
•
•
•
•
•
•
•
•
•
Four differential LVPECL output pairs
Selectable differential CLK/nCLK or crystal oscillator interface
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLK input
Additive phase jitter, RMS: TBD
Output skew: 25ps (typical)
Part-to-part skew: 150ps (typical)
Propagation delay: 1.5ns (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Guaranteed output and part-to-part skew characteristics make the
ICS8533I-31 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
CLK_EN
Pullup
D
Q
CLK
Pulludown
nCLK
Pullup
LE
0
Q0
nQ0
XTAL_IN
Q1
Pin Assignment
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL_IN
XTAL_OUT
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
OSC
XTAL_OUT
CLK_SEL
Pulludown
1
nQ1
Q2
nQ2
Q3
nQ3
ICS8533I-31
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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Test/Measurement
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