vided by an active LOW Chip Enable (CE) and three-state driv-
ers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (D
IN
) is written into the memory location specified on
the address pins (A
0
through A
15
).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied on the address pin will appear on the data output (D
OUT
)
pin.
The output pin stays in high-impedance state when Chip En-
able (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C187 is a high-performance CMOS static RAM orga-
nized as 65,536 words x 1 bit. Easy memory expansion is pro-
Logic Block Diagram
Pin Configurations
DI
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
NC
A
6
A
7
D
OUT
WE
GND
SOJ
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
15
A
14
A
13
A
12
NC
A
11
A
10
A
9
A
8
D
IN
CE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
OUT
WE
GND
DIP
Top View
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
D
IN
CE
A
12
A
13
A
14
A
15
A
0
A
1
A
2
A
3
ROW DECODER
256 x 256
ARRAY
SENSE AMPS
DO
C187–3
C187–2
CE
COLUMN DECODER
POWER
DOWN
WE
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
C187–1
Selection Guide
[1]
7C187-15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C187A datasheet.
7C187-20
20
80
40/20
7C187-25
25
70
20/20
7C187-35
35
70
20/20
15
90
40/20
Cypress Semiconductor Corporation
Document #: 38-05044 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C187
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 11) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
............................................ –0.5V to +7.0V
DC Input Voltage
[2]
.........................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C187-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE Power-
Down Current
[4]
Automatic CE
Power-Down Current
GND
<
V
I
<
V
CC
GND
<
V
O
<
V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
, CE
≥
V
IH
Max. V
CC
,
CE
≥
V
CC
– 0.3V,
V
IN
≥
V
CC
– 0.3V
or V
IN
≤
0.3V
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
=12.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
90
40
20
2.2
–0.5
–5
–5
Max.
7C187-20
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
80
40
20
2.2
–0.5
–5
–5
Max.
7C187-25, 35
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
70
20
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
2. V
IL
(min.) = –3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05044 Rev. **
Page 2 of 9
CY7C187
AC Test Loads and Waveforms
R1 329
Ω
(480
Ω
MIL)
R1 329
Ω
(480
Ω
MIL)
ALL INPUT PULSES
3.0V
R2 202
Ω
(R1 255
Ω
MIL)
GND
10%
90%
90%
10%
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
5V
OUTPUT
R2 202
Ω
5 pF
(R1 255
Ω
MIL)
INCLUDING
JIG AND
SCOPE
≤
5 ns
≤
5 ns
C187–5
(a)
(b)
C187–4
THÉ VENIN EQUIVALENT
OUTPUT
167
Ω
125
Ω
1.73V
OUTPUT
1.90V
Military
Commercial
Switching Characteristics
Over the Operating Range
[6]
7C187-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[8]
15
12
12
0
0
12
10
0
5
7
20
15
15
0
0
15
10
0
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
0
15
3
8
0
20
3
15
5
8
15
15
5
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C187-20
Min.
Max.
Unit
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
8. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05044 Rev. **
Page 3 of 9
CY7C187
Switching Characteristics
Over the Operating Range
[6]
(continued)
7C187-25
Parameters
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low
WE LOW to High Z
[8]
20
20
20
0
0
15
10
0
5
7
25
25
25
0
0
20
15
0
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
CE LOW to Low Z
[7]
CE HIGH to High Z
[7, 8]
CE LOW to Power Up
CE HIGH to Power Down
0
20
5
10
0
20
5
25
5
15
25
25
5
35
35
35
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C187-35
Min.
Max.
Units
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C187–6
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected, CE = V
IL
.
Document #: 38-05044 Rev. **
Page 4 of 9
CY7C187
Switching Waveforms
Read Cycle No. 2
[10, 12]
t
RC
CE
t
ACE
t
LZCE
DATA OUT
HIGH IMPEDANCE
DATA VALID
t
PD
ICC
50%
50%
ISB
C187–7
t
HZCE
HIGH
IMPEDANCE
V
CC
SUPPLY
CURRENT
t
PU
Write Cycle No. 1 (WE Controlled)
[11]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA VALID
t
HZWE
DATA OUT
DATA UNDEFINED
C187–8
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Write Cycle No. 2 (CE Controlled)
[11, 13]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA VALID
t
HD
t
HA
t
SCE
DATA OUT
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
京公网安备 11010802033920号
EEWORLD
