K4H510438G
K4H510838G
K4H511638G
DDR SDRAM
512Mb G-die DDR SDRAM Specification
60 FBGA
with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.0 October 2009
K4H510438G
K4H510838G
K4H511638G
DDR SDRAM
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description ...........................................................................................................................5
5.0 Package Physical Dimension ....................................................................................................6
6.0 Block Diagram (32Mbit x4 / 16Mbit x8 / 8Mbit x16 I/O x4 Banks).............................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table.................................................................................................................9
9.0 General Description...................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0 DC Operating Conditions ........................................................................................................10
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
DDR SDRAM IDD Spec Items & Test Conditions ..................................................................11
Input/Output Capacitance ......................................................................................................11
Detailed Test Condition for DDR SDRAM IDD1 & IDD7A ....................................................12
DDR SDRAM IDD Spec Table .................................................................................................13
AC Operating Conditions .......................................................................................................14
AC Overshoot/Undershoot Specification for Address and Control Pins ..........................14
Overshoot/Undershoot Specification for Data, Strobe and Mask Pins ..............................15
AC Timming Parameters & Specifications ...........................................................................16
System Characteristics for DDR SDRAM ..............................................................................17
Component Notes ....................................................................................................................18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
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Rev. 1.0 October 2009
K4H510438G
K4H510838G
K4H511638G
DDR SDRAM
Year
2009
- Initial Release
History
Revision History
Revision
1.0
Month
October
3 of 24
Rev. 1.0 October 2009
K4H510438G
K4H510838G
K4H511638G
DDR SDRAM
1.0 Key Features
• V
DD
: 2.5V ± 0.2V, V
DDQ
: 2.5V ± 0.2V for DDR333
• V
DD
: 2.6V ± 0.1V, V
DDQ
: 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
Lead-Free & Halogen-Free
package
•
RoHS compliant
2.0 Ordering Information
Part No.
K4H510438G-HC/LCC
K4H510438G-HC/LB3
K4H510838G-HC/LCC
K4H510838G-HC/LB3
K4H511638G-HC/LCC
K4H511638G-HC/LB3
Org.
128M x 4
64M x 8
32M x 16
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
SSTL2
SSTL2
SSTL2
Package
60ball FBGA
Lead-Free & Halogen-Free
60ball FBGA
Lead-Free & Halogen-Free
60ball FBGA
Lead-Free & Halogen-Free
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
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Rev. 1.0 October 2009
K4H510438G
K4H510838G
K4H511638G
DDR SDRAM
4.0 Ball Description
(Top
View)
128M x 4
9
8
7
3
2
1
V
DDQ
NC
V
DD
A
V
SS
NC
V
SSQ
NC
V
SSQ
DQ0
B
DQ3
V
DDQ
NC
NC
V
DDQ
NC
C
NC
V
SSQ
NC
NC
V
SSQ
DQ1
D
DQ2
V
DDQ
NC
NC
V
DDQ
NC
E
DQS
V
SSQ
NC
NC
V
DD
NC
F
DM
V
SS
V
REF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
V
DD
M
V
SS
A4
64M x 8
9
8
7
3
2
1
V
DDQ
DQ0
V
DD
A
V
SS
DQ7
V
SSQ
NC
V
SSQ
DQ1
B
DQ6
V
DDQ
NC
NC
V
DDQ
DQ2
C
DQ5
V
SSQ
NC
NC
V
SSQ
DQ3
D
DQ4
V
DDQ
NC
NC
V
DDQ
NC
E
DQS
V
SSQ
NC
NC
V
DD
NC
F
DM
V
SS
V
REF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
V
DD
M
V
SS
A4
32M x 16
9
8
7
3
2
1
V
DDQ
DQ0
V
DD
A
V
SS
DQ15
V
SSQ
DQ1
V
SSQ
DQ2
B
DQ13
V
DDQ
DQ14
DQ3
V
DDQ
DQ4
C
DQ11
V
SSQ
DQ12
DQ5
V
SSQ
DQ6
D
DQ9
V
DDQ
DQ10
DQ7
V
DDQ
LDQS
E
UDQS
V
SSQ
DQ8
NC
V
DD
LDM
F
UDM
V
SS
V
REF
CAS
WE
G
CK
CK
CS
RAS
H
CKE
A12
BA0
BA1
J
A9
A11
A10/AP
A0
K
A7
A8
A1
A2
L
A5
A6
A3
V
DD
M
V
SS
A4
Organization
128Mx4
64Mx8
32Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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Rev. 1.0 October 2009
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