and after a 10-minute warm-up unless otherwise noted.
DAC725JP
PARAMETER
INPUT
DIGITAL INPUT
Resolution
Bipolar Input Code
Logic Levels
(1)
: V
IH
V
IL
I
IH
(V
I
= +2.7V)
I
IL
(V
I
= +0.4V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
Differential Linearity Error
(3)
At Bipolar Zero: KP
(3, 4)
Gain Error
(5)
Bipolar Zero Error
(5)
Montonicity Over Specified Temp. Range
Power Supply Sensitivity: +V
CC
, –V
CC
V
DD
DRIFT
(Over Specified Temperature Range)
Gain Drift
Bipolar Zero Drift
Differential Linearity Over Temperature
(3)
Linearity Error Over Temperature
(3)
SETTLING TIME
(to
±0.003%
of FSR)
(6)
20V Step (2kΩ load)
1LSB Step at Worst-Case Code
(7)
Slew Rate
OUTPUT
Output Voltage Range
(8)
Output Current
Output Impedance
Short Circuit to Common Duration
POWER SUPPLY REQUIREMENTS
Voltage: +V
CC
–V
CC
V
DD
Current (No load,
±15V
supplies): +V
CC
–V
CC
V
DD
Power Dissipation (±15V supplies)
TEMPERATURE RANGE
Specification
Storage
*Specification same as model to the left.
NOTES: (1) Digital inputs are TTL, LSTTL, 54/74HC and 54/74HTC compatible over the specification temperature range. (2) FSR means Full-Scale Range. For
example, for
±10V
output, FSR = 20V. (3)
±0.0015%
of FSR is equal to 1LSB in 16-bit resolution.
±0.003%
of FSR is equal to 1LSB in 15-bit resolution.
±0.006%
of FSR is equal to 1LSB in 14-bit resolution. (4) Error at input code 0000
H
(BTC). (5) Adjustable to zero with external trim potentiometer. Adjusting the gain
potentiometer rotates the transfer function around the bipolar zero point. (6) Maximum represents the 3σ limit. Not tested for this parameter. (7) The bipolar worst-
case code change is FFFF
H
to 0000
H
(BTC). (8) Minimum supply voltage for
±10V
output swing is approximately
±13V.
Output swing for
±12V
supplies is at least
±9V.
0
–60
+70
+150
*
*
*
*
°C
°C
+11.4
–11.4
+4.5
+15
–15
+5
+29
–35
+6
920
+16.5
–16.5
+5.5
+35
–40
+10
1175
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
V
V
mA
mA
mA
mW
±10
±5
0.15
Indefinite
*
*
*
*
V
mA
Ω
±0.003
±0.0045
±0.07
±0.05
13
±0.0015
±0.0001
±10
±5
±0.0045
±0.006
±0.001
±0.006
±0.012
±0.2
±0.1
14
*
*
*
*
±0.003
*
*
±25
±12
±0.006
±0.006
8
4
±0.0015
0.003
±0.003
*
*
±0.003
±0.006
±0.006
±0.15
*
% of FSR
(2)
% of FSR
% of FSR
%
% of FSR
Bits
% of FSR/%V
CC
% of FSR/%V
DD
ppm/°C
ppm of FSR/°C
% of FSR
% of FSR
µs
µs
V/µs
16
Binary Twos Complement
+2
–1
+5.5
+0.8
1
1
*
*
*
*
*
*
*
V
V
µA
µA
*
Bits
MIN
TYP
MAX
MIN
DAC725KP
TYP
MAX
UNITS
±0.012
±0.012
4
2.5
10
*
*
*
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC725
2
CONNECTION DIAGRAM
PIN DESCRIPTIONS
PIN
1
DESIGNATOR
CLR
DESCRIPTION
Clear line. Sets the D/A
register to 0000
HEX
,
which gives bipolar zero
on the D/A output.
Logic supply (+5V).
Latch enable for D/A latch
(active low).
Latch enable for “low byte”
input (active low).
Latch enable for “high byte”
input (active low).
Input for data bit 7 if en-
abling low byte (LB) latch,
or data bit 15 if enabling
the high byte (HB) latch.
Input for data bit 6 if en-
abling LB latch, or data bit
14 if enabling HB latch.
Data bit 5 (LB) or data bit
13 (HB).
Data bit 4 (LB) or data bit
12 (HB).
Data bit 3 (LB) or data bit
11 (HB).
Data bit 2 (LB) or data bit
10 (HB).
Data bit 1 (LB) or data bit 9
(HB).
Data bit 0 (LB) or data bit
8 (HB).
Digital common.
Voltage output for DAC B.
Analog common for DAC B.
Summing junction of the in-
ternal op amp for DAC B.
Gain adjust pin for DAC B.
Write control line for DAC B.
Chip select control line for
DAC B.
Positive supply voltage
(+15V).
Negative supply voltage
(–15V).
Chip select control line for
DAC A.
Write control line for DAC A.
Voltage output for DAC A.
Analog common for DAC A.
Summing junction of the in-
ternal op amp for DAC A.
Gain adjust pin for DAC A.
CLR
V
DD
A
2
A
0
A
1
D
7
(D
15
)
D
6
(D
14
)
D
5
(D
13
)
D
4
(D
12
)
D
3
(D
11
)
D
2
(D
10
)
D
1
(D
9
)
D
0
(D
8
)
DCOM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
High
Byte
Latch
Low
Byte
Latch
8
28
27
26
8
D/A
16
Latch
16-
Bit
D/A
25
24
23
22
21
20
19
18
8
D/A
16
Latch
Low
Byte
Latch
8
15
16-
Bit
D/A
17
16
GA (A)
SJ (A)
ACOM
(A)
V
OUT
(A)
2
3
4
5
6
V
DD
A
2
A
0
A
1
D
7
(D
15
)
(MSB)
High
Byte
Latch
WR (A)
CS (A)
–V
CC
7
D
6
(D
14
)
8
+V
CC
D
5
(D
13
)
D
4
(D
12
)
D
3
(D
11
)
D
2
(D
10
)
D
1
(D
9
)
D
0
(D
8
)
DCOM
V
OUT
(B)
ACOM (B)
SJ (B)
GA (B)
WR (B)
CS (B)
+V
CC
–V
CC
CS (A)
WR (A)
V
OUT
(A)
ACOM (A)
SJ (A)
GA (A)
9
CS (B)
WR (B)
GA (B)
SJ (B)
ACOM
(B)
V
OUT
(B)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ABSOLUTE MAXIMUM RATINGS
V
DD
to COMMON ........................................................................ 0V, +15V
+V
CC
to COMMON ...................................................................... 0V, +18V
–V
CC
to COMMON ...................................................................... 0V, –18V
Digital Data Inputs to COMMON ...................................... –0.5V, V
DD
+ 0.5
DC Current any Input ......................................................................
±10mA
Reference Out to COMMON ........................ Indefinite Short to COMMON
V
OUT
............................................................ Indefinite Short to COMMON
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