3.2 mm x 2.5 mm Ceramic Package SMD VCXO
LVCMOS / LVPECL / LVDS
I642 Series
Product Features
Small Surface Mount Package
Fast Sample Delivery
Fast Sample Delivery
Pb Free/ RoHS Compliant
Leadfree Processing
Applications
xDSL
Broadcast Video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
3.20±0.10
Marking
2.50±0.10
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage (Vcc)
Aging
Current
10.000MHz to 250.000MHz
10.000MHz to 1500.000MHz
10.000MHz to 1500.000MHz
Logic “0” = 10% of Vcc max, Logic “1” = 90% of Vcc min
Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50% of Vcc
50% ±5% @ 50%*
50% ±5% @ 50%*
2.0 ns max. (10% to 90%)*
0.8 ns max. (20% to 80%)*
0.8 ns max. (20% to 80%)*
.70
1.00±0.15
.60
TYP
1
2
3
1.30
TYP
6
5
4
1.60
2.30
Linearity
Pullability
Control Voltage
Input Impedance
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp. Range
Storage Temp. Range
15pF
50
to Vcc - 2.0 VDC
RL=100
/CL=
5pF
See Table Below
+3.30 VDC ± 5%, +2.50 VDC ± 5%
±3.0 ppm max per year
HCMOS = 45 mA max
LVPECL = 90 mA max
LVDS = 35 mA max
10% max.
See Table Below
1.65 VDC ± 1.65 VDC @ 3.3V
1.25 VDC ± 1.25 VDC @ 2.5V
50K
min.
0.9 ps typical
See Table Below
-40
C to +85
C
1.80
.90
.80
Suggested Land Pattern
PIN CONNECTIONS
Voltage Control
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
Enable/Disable
or N/C
Ground
Output
Comp. Output
or N/C
Voltage Supply
.90
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Stability
(in ppm)
F =
20
A =
25
B =
50
I642–31AB9H2–155.520
Enable / Disable
(Pin 2)
H = Enable
O = N/C
Operating
Temperature
1 = 0 C to +70 C
2 = -40 C to +85 C
3 = -20 C to +70 C
Pullabilty
B =
50
C =
100
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
I642
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI America Phone 775-851-8880
●
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
●
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 03/10/15_A
Page 1 of 3
3.2 mm x 2.5 mm Ceramic Package SMD VCXO
LVCMOS / LVPECL / LVDS
I642 Series
SSB Phase Noise (typ.)
Offset
10Hz
100Hz
1kHz
10kHz
100kHz
77.76 MHz
-75 dBc/Hz
-105 dBc/Hz
-117 dBc/Hz
-123 dBc/Hz
-125 dBc/Hz
155.52 MHz
-62 dBc/Hz
-101 dBc/Hz
-112 dBc/Hz
-115 dBc/Hz
-118 dBc/Hz
622.08 MHz
-47 dBc/Hz
-79 dBc/Hz
-100 dBc/Hz
-104 dBc/Hz
-106 dBc/Hz
Typical Application:
Vcc
N/C
C1
0.01
uF
Output
6
5
4
Oscillator
Vc
Enable / N/C
1
2
3
Pb Free Solder Reflow Profile:
*Units are backward compatible with 240C reflow processes
Package Information:
MSL = N.A. (package does not contain plastic, storage life is unlimited under normal room conditions).
Termination = e4 (Au over Ni over W base metallization).
ILSI America Phone 775-851-8880
●
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
●
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 03/10/15_A
Page 2 of 3
3.2 mm x 2.5 mm Ceramic Package SMD VCXO
LVCMOS / LVPECL / LVDS
I642 Series
Tape and Reel Information:
Quantity per
Reel
A
B
C
D
E
F
1000
16 +/-.3
8 +/-.2
7.5 +/-.2
17.5 +/-1
50 / 60 / 80
180 / 250
Environmental Specifications
Thermal Shock
Moisture Resistance
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Hazardous Substance
Solderability
Terminal Strength
Gross Leak
Fine Leak
Solvent Resistance
MIL-STD-883, Method 1011, Condition A
MIL-STD-883, Method 1004
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2007, Condition A
J-STD-020C, Table 5-2 Pb-free devices (except 2 cycles max)
Pb-Free / RoHS / Green Compliant
JESD22-B102-D Method 2 (Preconditioning E)
MIL-STD-883, Method 2004, Test Condition D
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 1014, Condition A2, R1=2x10-8 atm cc/s
MIL-STD-202, Method 215
Marking
Line 1: ILSI and Date Code (YWW)
Line 2: Frequency
PROPRIETARY AND CONFIDENTIAL
THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION, AND SUCH INFORMATION MAY NOT BE DISCLOSED TO OTHERS FOR ANY
PURPOSE NOR USED FOR MANUFACTURING PURPOSES WITHOUT WRITTEN PERMISSION FROM ILSI America.
ILSI America Phone 775-851-8880
●
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
●
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 03/10/15_A
Page 3 of 3
Automotive Electronics
京公网安备 11010802033920号
EEWORLD
