E
n
n
n
n
n
n
n
DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
n
Revolutionary Architecture
100% Backwards-Compatible with
Intel 28F016SA
Pipelined Command Execution
Program during Erase
2 mA Typical I
CC
in Static Mode
2 µA Typical Deep Power-Down
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
User-Selectable 3.3V or 5V V
CC
User-Configurable x8 or x16 Operation
70 ns Maximum Access Time
28.6 MB/sec Burst Write Transfer Rate
1 Million Typical Erase Cycles per Block
56-Lead, 1.2 x 14 x 20 mm Advanced
Dual Die TSOP Package Technology
64 Independently Lockable Blocks
n
n
n
Intel’s DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative
capabilities, low power operation and very high read/program performance, the DD28F032SA is also the ideal
choice for designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly-advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/program solution for solid-
state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F016SA
16-Mbit FlashFile memory), very high-cycling, low-power 3.3V operation, very fast program and read
performance and selective block locking provide a highly flexible memory component suitable for high-density
memory cards, Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA’s dual read voltage
enables the design of memory cards which can be read/written in 3.3V and 5.0V systems interchangeably. Its
x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option
enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel’s 0.6 µm ETOX IV technology.
December 1996
Order Number: 290490-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
E
DD28F032SA
CONTENTS
PAGE
PAGE
6.0 ELECTRICAL SPECIFICATIONS..................19
6.1 Absolute Maximum Ratings........................19
6.2 Capacitance ...............................................20
6.3 Timing Nomenclature .................................21
6.4 DC Characteristics (V
CC
= 3.3V ± 0.3V) .....24
6.5 DC Characteristics (V
CC
= 5.0V ± 0.5V) ....26
6.6 AC Characteristics—Read Only
Operations ...................................................28
6.7 Power-Up and Reset Timings.....................32
6.8 AC Characteristics for WE#—Controlled
Command Write Operations .........................33
6.9 AC Characteristics for CE
X
#—Controlled
Write Operations ..........................................37
6.10 AC Characteristics for Page Buffer Write
Operations ...................................................41
6.11 Erase and Word/Byte Program
Performance, Cycling Performance and
Suspend Latency .........................................44
7.0 DERATING CURVES ....................................45
8.0 MECHANICAL SPECIFICATIONS ................47
APPENDIX A: Device Nomenclature/
Ordering Information .....................................48
APPENDIX B: Additional Information...............49
1.0 PRODUCT OVERVIEW................................... 5
2.0 DEVICE PINOUT............................................. 6
2.1 Lead Descriptions ........................................ 8
3.0 MODES OF OPERATION ............................. 10
4.0 MEMORY MAPS ........................................... 11
4.1 Extended Status Registers Memory Map ... 12
5.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS................ 13
5.1 Bus Operations for Word-Wide Mode
(BYTE# = V
IH
).............................................. 13
5.2 Bus Operations for Byte-Wide Mode
(BYTE# = V
IL
) .............................................. 13
5.3 28F008SA Compatible Mode Command
Bus Definitions ............................................. 14
5.4 28F016SA-Performance Enhancement
Command Bus Definitions............................ 15
5.5 Compatible Status Register ....................... 16
5.6 Global Status Register ............................... 17
5.7 Block Status Register ................................ 18
3
DD28F032SA
E
REVISION HISTORY
Description
—Original Version
—Never Published
—Full Datasheet with Specifications
—CE
0
#, CE
1
# control 28F016SA No. 1
—CE
0
#, CE
2
# control 28F016SA No. 2
—DC Characteristics (3.3V V
CC
): I
CCR1
(TTL): BYTE# = V
IL
or V
IH
—Full Chip Erase Time (3.3V V
CC
) = 51.2 sec typ
—Full Chip Erase Time (5.0V V
CC
) = 38.4 sec typ
—Section 6.7: Added specifications t
PHEL3
, t
PHEL5
—TSOP dimension A
1
= 0.05 mm (min)
—Revised Product Status to Preliminary
—t
WHGL
(3.3V) = 120 ns
—Minor cosmetic changes
—Updated AC/DC parameters
Number
-001
-002
-003
-004
-005
4
E
DD28F032SA
These new commands and features include:
•
Page Buffer Writes to Flash
•
Command Queueing Capability
•
Automatic Data Programs during Erase
•
Software Locking of Memory Blocks
•
Two-Byte
Systems
Successive
Programs
in
8-bit
1.0 PRODUCT OVERVIEW
The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonvolatile random
access memory organized as either 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using
two 28F016SA chips encapsulated in a single
56- lead TSOP Type I package. The DD28F032SA
includes sixty-four 64-KB (65,536) blocks or sixty-
four 32-KW (32,768) blocks.
The DD28F032SA architecture allows operations
to be performed on a single, 16-Mbit chip at a
time.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and results in greater
product reliability and ease of use.
Among the significant enhancements on the
DD28F032SA:
•
3.3V Low Power Capability
•
Improved Program Performance
•
Dedicated Block Program/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/program
operation.
The DD28F032SA will be available in a 56-lead,
1.2 mm thick, 14 mm x 20 mm Dual Die TSOP
Type I package. This form factor and pinout allow
for very high board layout densities. The
DD28F032SA is pinout and footprint compatible
with the 28F016SA.
Two Command User Interfaces (CUI) serve as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal algorithm automation allows word/byte
programs and block erase operations to be
executed using a two-write command sequence to
the CUI in the same way as the 28F016SA
16-Mbit FlashFile memory.
A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory)
command-set to achieve higher program
performance and provide additional capabilities.
•
Erase All Unlocked Blocks
These operations can only be performed on one
16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not
attempt to select the other device.
Writing of memory data is performed in either byte
or word increments typically within 6 µs, a 33%
improvement over the 28F008SA. A block erase
operation erases one of the 64 blocks in typically
0.6 sec, independent of the other blocks, which is
a 65% improvement over the 28F008SA.
Each block can be written and erased a minimum
of 100,000 cycles. Systems can achieve typically
1 million block erase cycles by providing wear-
leveling algorithms and graceful block retirement.
These techniques have already been employed in
many flash file systems. Additionally, wear leveling
of block erase cycles can be used to minimize the
program/erase performance differences across
blocks.
The DD28F032SA incorporates two Page Buffers
of 256 bytes (128 words) on each 28F016SA to
allow page data programs. This feature can
improve a system program performance by up to
4.8 times over previous flash memory devices.
All operations are started by a sequence of
command writes to the device. Three Status
Registers (described in detail later) and a RY/BY#
output pin provide information on the progress of
the requested operation.
The DD28F032SA allows queueing of the next
operation while the memory executes the current
operation. This eliminates system overhead when
writing several bytes in a row to the array or
erasing several blocks at the same time. The
DD28F032SA can also perform program
operations to one block of memory while
performing erase of another block. However,
simultaneous program and/or erase operations are
not allowed on both 28F016SA devices. See
Modes of Operation, Section 3.0.
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
